Solid state imaging device with horizontal transfer paths and a driving method therefor

ABSTRACT

In a solid state imaging device, signal charges are branched to be output to in the form of one or plural outputs. At a horizontal transfer speed not lower than a predetermined transfer speed, the imaging device transfers signal charges of color attributes classified by a branching section, to plural horizontal transfer paths, where the signal charges are converted into analog voltage signals, which will be output synchronously. At a horizontal transfer speed lower than the predetermined transfer speed, the analog voltage signal converted is output from, e.g. the horizontal transfer path which has been selected. Output amplifiers arranged on the horizontal transfer paths are differentiated in sensitivities in detecting signal charges, depending on color attributes of signal charges supplied, and output the analog voltage signals.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of co-pending application Ser. No.11/727,139 filed Mar. 23, 2007 the entire contents of which are herebyincorporated by reference and for which priority is claimed under 35U.S.C. §120.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a solid-state imaging device and adriving method therefor. More particularly, the present inventionrelates to a solid-state imaging device such as a CCD (Charge-CoupledDevice) imaging device for transducing incident light into signalcharges and horizontally transferring the charges to output an imagesignal through an output amplifier. The invention also more specificallyrelates to a driving method of driving the imaging device for horizontaltransfer.

2. Description of the Background Art

Japanese patent laid-open publication No. 50409/1995 disclosesbifurcating a sole transfer path, that is, a shift register, andproviding an amplifier at the distal end of each bifurcated transferpath. Each amplifier is a floating diffusion amplifier (FDA) and differsfrom one another in charge detection sensitivity or charge-to-voltageconversion efficiency. When a subject being imaged is of lowerluminance, the higher-efficiency amplifier outputs the output signal.This amplifier selection improves the voltage conversion efficiency forlower signal charges obtained on light reception, and raises thesensitivity. When the subject being imaged is of higher luminance, thelower-efficiency amplifier outputs the output signal. With the use ofthis amplifier, the image generated by the output signal is of a widerdynamic range. Another Japanese patent laid-open publication No.298626/1996 is substantially similar to the '409 publication.

Still another Japanese patent laid-open publication No. 244340/1993 alsoteaches bifurcating a sole transfer path, or a shift register. However,the signal charges obtained on light reception or optical sensing arealternately switched at the bifurcating section and transferred to therespective amplifiers. The frequency of the driving pulse supplied tothe transfer path not bifurcated is twice as high as the driving pulsesupplied to the bifurcated transfer paths. In other words, a drivingfrequency one-half the usual driving frequency suffices for driving thebifurcated transfer paths. Thus, the amplifier renders it possible toraise the transfer speed as the driving frequency is maintained withinthe frequency band prescribed as its operating characteristics.

In the '409 and '626 publications, there is simply disclosed guiding thesignal charges to a selected transfer path. The '340 publicationdiscloses alternately outputting signal charges. If those publicationsare simply combined together, it would indeed be possible to outputimages that satisfy the requirements for high sensitivity and widedynamic range.

In producing a color image, color attributes are allocated to therespective signal charges. However, there is neither suggestion nordisclosure as to how the signal charges are transferred and distributedto the bifurcated transfer paths from color to color. Thus, with thoseprior art publications combined together, it would not be possible toprovide an image reduced in noise based on a white-balance gain withrespect to color.

If with the conventional solid state imaging device a subject with lowercolor temperature, for example, is shot, then the amounts of signalcharges obtained in the photosensitive cells of the imaging device arelarger for red (R) pixels and smaller for blue (B) pixels. If the signalcharge are horizontally transferred from the transfer path notbifurcated in the sequence of an R pixel, a first green (G1) pixel, a Bpixel and a second green (G2) pixel, the amount of charges left over bythe forward R pixel and mixed into the rear side G1 pixel is greaterthan the amount of charge mixing between the forward side B pixel andthe rear side G2 pixel. Thus, the G1 and G2 pixels which are of the samecolor signal differ in the signal quantity, thus affecting the finishedimage as a fixed pattern noise.

In addition, deterioration in the transfer efficiency of signal chargesis caused with the solid state imaging device in which signal chargesare not branched optimally at a branching electrode such that signalcharges to be sent to one of the horizontal transfer paths are intrudedinto the other transfer path.

More specifically, such a case is now considered in which signal chargesare transferred from a sole horizontal transfer path in the sequence ofa G1 pixel, an R pixel, a G2 pixel and a B pixel, and are branched atthe branching electrode, signal charges of the pixels G1 and G2 are sentto one of the horizontal transfer paths and those of the pixels R and Bare sent to the other transfer path. If the ambient temperature at thetime of imaging is low, part of signal charges of the pixel G1 is mixedinto signal charges of the pixel R.

Such deterioration in the transfer efficiency, i.e., transferdeterioration, of signal charges is caused not only when the ambienttemperature at the time of imaging is low, but also when the colortemperature of a subject being imaged is low or the ISO (InternationalOrganization for Standardization) sensitivity is high. In particular, incase of a subject with a low color temperature, signal charges are mixedin different quantities, even if the signal charges are of the samecolor. More specifically, supposing that signal charges of pixels G1, R,G2 and B obtained on imaging a subject of a low color temperature aretransferred in that order, the signal charges are mixed in the pixel Rfrom the pixel G1 in larger quantity than the quantity of the signalcharges mixed from the pixel G2 into the pixel B. The result is thatsignal quantities of the pixels R and B become different from eachother, with the difference in signal quantity then being visualized asnoise in the image.

In the meantime, in those prior art publications, there is neithersuggestion nor disclosure as to the sequence of readout of color signalsor as to how signal charges are to be split to the branched transferpaths depending on the colors. It is noted that, if the branchingsection receives signals of different colors, and cannot correctlytransfer the signal charges to the branches, part of those signals ofdifferent colors may be mixed with each other on the branches.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a solid stateimaging device and a driving method therefor with which it is possibleto branch signal charges to output the so branched signal charges oneither one or plural paths, as well as to achieve the noise reductionbased on the white balance gain.

It is another object of the present invention to provide a solid stateimaging device and a driving method therefor in which the ill effect oftransfer deterioration ascribable to the bifurcation may be moderatedeven with the use of an imaging device having its horizontal transferpath bifurcated partway to output signal charges in either one or pluralpaths, thereby enabling an optimum image to be produced.

It is still another object of the present invention to provide a drivingmethod for a solid state imaging device which is free from deteriorationin the transfer efficiency at the branching electrode and is capable ofproducing an optimal image, as well as to provide a driving method foruse in an imaging apparatus including the solid state imaging device.

It is yet another object of the present invention to provide a solidstate imaging apparatus and an imaging method, in which, even in casethe branching section cannot correctly transfer signal charges, signalmixing between different colors is minimized.

In accordance with the present invention, there is provided a solidstate imaging device including a two-dimensional array of photosensitivecells, a first horizontal transfer circuit for transferring signalcharges, a branching circuit, a plurality of second horizontal transfercircuits, and a plurality of output circuits. The photosensitive cellsare supplied with incident light from a field being imaged, via colorfilter segments adapted for color separating the incident light. Thephotosensitive cells operate for transducing the light transmittedthrough the color filter segments into electrical signals depending onthe volume of transmitted light. The first horizontal transfer circuitoperate for transferring signal charges having color attributes, readout from each of the photosensitive cells and transferred in a verticaldirection, in a horizontal direction perpendicular to the verticaldirection. The branching circuit is arranged adjacent to an output endof the first horizontal transfer circuit for transiently holding thesignal charges transferred and for distributing the signal charges to aplurality of output destinations related with the color attributes ofthe signal charges. The second horizontal transfer circuits areconnected to the branching circuit as branching destinations. The outputcircuits are each provided at an output end of each of the secondhorizontal transfer circuits. The output circuits each operate forconverting the signal charges into an analog voltage signal responsiveto detection of the signal charges to amplify the analog voltage signal.The signal charges supplied to the branching circuit at a horizontaltransfer speed during horizontal transfer not lower than a predeterminedtransfer speed are classified depending on the color attributes andtransferred to each of the second horizontal transfer circuits. Thesignal charges supplied from the output circuits are converted intoanalog voltage signals which are output. The analog voltage signals areoutput from selected horizontal transfer circuit with transfer at ahorizontal transfer speed lower than the predetermined transfer speed.The plural output circuits exhibit differential detection sensitivitiesfor the signal charges depending on the color attributes of the signalcharges supplied. The output circuits output the analog voltage signals.

With the solid state imaging device according to the present invention,signal charges of the color attributes, classified in the branchingcircuit, are transferred to each of a plural number of horizontaltransfer means for horizontal transfer with a horizontal transfer speednot lower than a predetermined speed. The analog voltage signals,converted from the signal charges, are output. For horizontal transferwith the horizontal transfer speed lower than the predetermined transferspeed, the analog voltage signals converted from the signal charges areoutput from the selected horizontal transfer circuit. As each of theoutput circuits associated with plural horizontal transfer means hasdifferential sensitivities in detecting the signal charges, depending onthe color attributes of the signal charges supplied thereto, it ispossible to modulate the sensitivities of the red and blue signals withrespect to those of the green signals to suppress unneeded gain andhence reduce the noise.

In accordance with the present invention, there is also provided amethod for driving a solid state imaging device for transferring signalcharges having color attributes. The solid state imaging device includesa plurality of vertical transfer circuits and horizontal transfercircuit. The vertical transfer circuits operate for reading out signalcharges having color attributes from each of photosensitive cells eachadapted for transducing incident light into an electrical signal. Thevertical transfer circuits transfer the read-out signal charges havingthe color attributes, in the vertical direction. The horizontal transfercircuit transfers the signal charges transferred from the verticaltransfer circuits, in the horizontal direction. The solid state imagingdevice also includes a plurality of horizontal transfer circuitsbranched from a transfer region adapted for branching signal chargesfrom the horizontal transfer circuit having color attributes. The pluralhorizontal transfer circuits exhibit differential detectionsensitivities to signal charges having the color attributes. The methodcomprises classifying the signal charges, supplied to the branchingtransfer region with high speed driving with the horizontal transferspeed not less than a predetermined transfer speed, according to thecolor attributes, sending the signal charges of the color attributes oneach of the plural horizontal transfer circuits, converting the signalcharges of the color attributes into analog voltage signals, outputtingthe analog voltage signals, outputting the analog voltage signals fromselected horizontal transfer circuit with low speed driving at ahorizontal transfer speed lower than the predetermined transfer speed,and adjusting the branched output destination of the signal chargeshaving color attributes by changing the phase of a driving pattern inhorizontal transfer, before branching, with respect to the driving in atleast one branched horizontal transfer.

With the method for driving the solid state imaging device, the pluralhorizontal transfer circuits exhibit differential detectionsensitivities to signal charges having the color attributes. Thebranched output destination of the signal charges having colorattributes may be adjusted by changing the phase of a driving pattern inhorizontal transfer, before branching, with respect to the driving in atleast one branched horizontal transfer. This renders it possible tofreely change the sensitivity in charge detection for signal chargessupplied and to set the gain flexibly in keeping with imaging conditionson hand. In this manner, data of high accuracy may be obtained toprovide a high-quality image.

In accordance with the present invention, there is also provided a solidstate imaging apparatus including a solid state imaging device. Thesolid state imaging device includes a plurality of photosensitive cells,a plurality of color filter segments, a vertical transfer circuit, afirst horizontal transfer circuit, a branching circuit, second and thirdtransfer circuits and first and second output circuits. Thephotosensitive cells are arrayed in a matrix of rows and columns forphoto-electrically transducing incident light from a field being imagedinto signal charges. The color filter segments are arranged in registerwith the photosensitive cells for color separating the incident lightinto plural colors to cause the light of the plural colors to beincident on the photosensitive cells. The vertical transfer circuitoperates for vertically transferring the signal charges read out fromthe photosensitive cells. The first horizontal transfer circuit operatesfor receiving the signal charges vertically transferred from thevertical transfer circuit to transfer the received signal chargeshorizontally. The branching circuit is arranged at an output end of thefirst horizontal transfer circuit for distributing the horizontallytransferred signal charges to an optional one of a plurality of outputdestinations. The second and third transfer circuits are adapted forreceiving the signal charges distributed from the branching circuit tofurther horizontally transfer the signal charges. The first and secondoutput circuits are arranged at output ends of the second and thirdtransfer circuits, respectively. The solid state imaging apparatuscomprises transfer efficiency measuring means for measuring the transferefficiency on the second and third transfer circuits in the course oftransfer of the signal charges from the branching circuit through thesecond and third transfer circuits to the first and second outputcircuits. The driving start time of a first drive signal for driving thefirst horizontal transfer circuit or a second drive signal for drivingthe second and third horizontal transfer circuits is changed dependingon the result of measurement by the transfer efficiency measuringcircuit. One of the second and third horizontal transfer circuits ispreferentially used to transfer the signal charges.

Thus, with the solid state imaging apparatus according to the presentinvention, when the signal charges obtained by the imaging unit from thephotosensitive cells, during high speed driving, are transferred via aplural number of vertical transfer paths to a first horizontal transferpath, and the signal charges horizontally transferred from the firsthorizontal transfer path are branched and transferred to the second andthird horizontal transfer paths, the phase of the horizontal timingsignal controlling the driving of the horizontal transfer path of theimaging unit is offset from that of the initial driving condition,depending on the results of measurement by the transfer efficiencymeasurement unit. By so doing, it is possible to interchange the signalcharges transferred to the second horizontal transfer path and thosetransferred to the third horizontal transfer path, by way of reversingthe branching.

Moreover, with the solid state imaging apparatus according to thepresent invention, signal charges of red and blue pixels are transferredon one of the second and third horizontal transfer paths which has ahigher transfer efficiency, during high speed driving, while those ofgreen pixels are transferred on the remaining horizontal transfer path.By so doing, the quantity of residual transfer charges from the red andblue pixels to the green pixels may be reduced to provide for an optimumimage.

With the solid state imaging apparatus according to the presentinvention, all signal charges are transferred during low speed drivingto the second or third horizontal transfer paths which has a highertransfer efficiency, depending on the results of measurement by thetransfer efficiency measurement unit. By so doing, the quantity ofresidual transfer charges of the pixels may be decreased to moderate anyadverse effect of transfer deterioration of the entire image to providefor an optimum image.

Furthermore, with the solid state imaging apparatus according to thepresent invention, the imaging unit switches between the outputdestinations of the second and third horizontal transfer paths,depending on the transfer efficiency. By so doing, there is no necessityof changing the wiring of the external circuit of the imaging unit evenif the output site of the color signals is changed between the secondand third horizontal transfer paths.

In accordance with the present invention, for accomplishing the aboveother object of the present invention, the duty cycle and/or the periodof the drive signal driving the transfer circuit before branching, whichis an electrode directly upstream of the branch electrode in the solidstate imaging device, is changed, or the duty cycle and/or the period ofthe drive signal driving the horizontal transfer path transferringbranched signal charges signal charges is changed, in order to providefor transfer time for signal charges from the electrode before branchingto the branch electrode longer than the usual transfer time, or fortransfer time from the branch electrode to the horizontal transfer pathtransferring branched signal charges longer than the usual transfertime.

In more detail, attention is directed in the present invention to thefact that, if part of signal charges of red and blue pixels is intrudedinto signal charges of the green pixels, the result is the noiserepresented on the image. Thus, the transfer time of signal charges ofred and blue pixels to the branch electrode from the electrode beforebranching or the transfer time of transfer to the horizontal transferpath of branched signal charges of red and blue pixels from the branchelectrode, is set so as to be longer than the usual value.

The usual transfer time is the transfer time prior to changing the dutycycle or the period of the drive signal, that is, the transfer time inwhich no transfer efficiency deterioration has occurred, viz, thetransfer time in which the transfer efficiency is maintained. Meanwhile,the duty cycle is the temporal relation between the periodicallyalternating high and low levels, and specifically is the ratio of thehigh level time of a signal in a signal period, or a duty ratio.

By providing for the transfer time during transfer of the signal chargesof the red and blue pixels longer than the usual transfer time, it ispossible to secure sufficient shifting of the signal charges. Hence, itis possible to prevent part of the signal charges of red and blue pixelsfrom being left over and mixing into the signal charges of the greenpixel.

The processing for providing for the transfer time longer than the usualtransfer time may be changed in dependence upon the temperature, colortemperature of the subject, sensitivity or the rate of reading outelectrical signals. How much the duty cycle or the period is to bechanged may be found by calculating the transfer efficiency, whichtransfer efficiency may be calculated using a reference signal charge.

According to the present invention, it is possible to preventdeterioration of the transfer efficiency in the branch electrode and toobtain an optimum image free of noise.

In accordance with the present invention there is also provided a solidstate imaging apparatus comprising a color filter, a plurality ofphotosensitive cells, a first transfer circuit, a second transfercircuit, a branching circuit, a plurality of third transfer circuits,and output circuits. The color filter operates for color separating theincident light from a field being viewed into a plurality of colors. Thephotosensitive cells operate for photo-electrically transducing thelight transmitted through the color filter. The photosensitive cells arearranged in register with the colors. The first transfer circuitoperates for transferring signal charges read out from thephotosensitive cells in a first direction. The second transfer circuitoperates for transferring signal charges read out from the firsttransfer means in a second direction. The branching circuit is arrangedat an output end of the second transfer circuit for distributing thesignal charges transferred to a plurality of output destinations. Thethird transfer circuits are connected as the output destinations to thebranching circuit, and the output circuits are connected to an outputend of the third transfer circuits. The plural colors are divided into aplurality of groups. The second transfer circuit, the branching circuitand the third transfer circuits transfer signal charges read out fromthe photosensitive cells related with colors of the same group, andsubsequently transfer signal charges read out from the photosensitivecells related with colors of a different group or groups.

According to the present invention, in case the second transfer circuit,for example, the horizontal transfer path, is branched partway,outputting is to be made at plural output parts, and the colorsbelonging to different groups, for example, red (R) and blue (B) on onehand and green (G) on the other hand, may be read out in a statecompletely isolated from each other. For example, in transferring Gsignals and RB signals contained in the same line or field, it ispossible to transfer the G signals contained in a given line or field,and subsequently to transfer the RB signals contained in the same lineor field. That is, the G signals and the RB signals contained in thesame line or field, may be separately read out as if these G signals andRB signals belong to a distinct line of field.

Hence, there is no fear that different colors alternately pass throughthe branching circuit, so that it is possible to prevent G signals frommixing into R and B signals or to prevent R and B signals from mixinginto the G signals, so as to provide an image in an optimum state. Thereason signal mixing is likely to be produced in branching circuit isthat it is necessary for the branching circuit to be able to transfersignal charges in plural directions and hence is larger in size or of aspecial profile other than a square with the result that signal chargescannot be transferred unobjectionably. For example, it may occur thatthe signal at a terminal part of branching circuit cannot betransferred.

According to the present invention, the signal charges transferred in alump as belonging to the same group are not necessarily the signalcharges of one line or field, and may be signal charges of more or lessthan one line or field. A plural number of lines or fields, one frame, aplural number of frames or one-half line of signal charges may betransferred in a lump.

In the present invention, if the plural colors are three colors of red,green and blue, it is preferred to provide two groups, namely a group ofred and blue and a group of green. The reason is that, even thoughsignal mixing occurs between red and blue, this state can be correctedrather easily.

If there are plural colors belonging to one of the groups, the signalcharges read out from the photosensitive cells related with therespective colors are preferably transferred from color to color usingspecified one of third transfer circuits. Since output circuits aredetermined from color to color, it is possible to prevent differentialintensities (step differences) between the same colors ascribable toindividual differences of the output parts.

In case signal charges are transferred using a plural number of thirdtransfer circuits, it is preferred to use correction circuit forcorrecting the difference in characteristics between the plural outputcircuits in order to correct the difference in characteristics betweenthe plural output circuits. This corrects the step difference of colorsascribable to individual differences of the output parts.

The present invention may be applied to an imaging method not exploitingbranching circuit. That is, the present invention may be applied to animaging method comprising color-separating incident light from a fieldbeing imaged by a color filter, photo-electrically transducing the lighttransmitted through the color filter by a plurality of photosensitivecells related with the colors, transferring signal charges read out fromthe photosensitive cells by first transfer circuit in a first direction,transferring the signal charges transferred by the first transfercircuit, by second transfer means in a second direction, and outputtingsignal charges via output circuits arranged at an output end of thesecond transfer circuit. The plural colors are divided into a pluralityof groups. The second transfer circuit transfers the signal charges readout from the photosensitive cells related with the color belonging tothe same group, and subsequently transfer signal charges read out fromthe photosensitive cells related with the color belonging to thedifferent group.

According to the present invention, there may be provided a solid stateimaging method and apparatus in which signal mixing may not be producedamong different colors even in case branching circuit cannotunobjectionably transfer signal charges.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects and features of the present invention will become moreapparent from consideration of the following detailed description takenin conjunction with the accompanying drawings in which:

FIG. 1 is a schematic block diagram showing a preferred embodiment of atwo-line readout CCD implemented as a solid state imaging deviceaccording to the present invention;

FIG. 2 is a schematic block diagram showing a preferred embodiment of adigital camera employing the solid state imaging device of FIG. 1;

FIG. 3 is a schematic block diagram showing drivers shown in FIG. 2;

FIG. 4, part (A) is a partial plan view looked from above, and showingthe schematic constitution of a horizontal transfer path in the solidstate imaging device of FIG. 1, part (B) is a cross-sectional view ofthe transfer path, taken along a section line IV-IV, and parts. (C) and(D) show how the potential changes in various parts of the horizontaltransfer path;

FIG. 5 is a timing chart showing the timing of drive signals supplied torespective electrodes of FIG. 4, parts (A) and (B);

FIG. 6, part (A) continuing from the lower part of FIG. 4 is across-sectional view of the transfer path, and parts (B), (C) and (D)show how the potential changes;

FIG. 7, part (A) is a partial plan view, looking from above, showing theschematic constitution of the horizontal transfer path in the device ofFIG. 1, part (B) is a cross-sectional view of the transfer path, takenalong a section line VII-VII, and parts (C) and (D) show how thepotential changes in various parts of the horizontal transfer path;

FIG. 8, part (A) continuing from the lower part of FIG. 7 is across-sectional view of the transfer path, and parts (B), (C) and (D)show how the potential changes;

FIGS. 9A to 9E are schematic views for illustrating the transfer ofsignal charge with color attributes over horizontal transfer paths inthe solid state imaging device of FIG. 1;

FIGS. 10A and 10B schematically show the difference in gate capacitancesin the output amplifier of FIG. 1;

FIGS. 11A and 11B schematically show the difference in film thicknessformed in the floating diffusion in the output amplifier of FIG. 1;

FIGS. 12A and 12B schematically show the difference in the surface areain the floating diffusion in the output amplifier of FIG. 1;

FIGS. 13A and 13B schematically show the presence and the absence of afilm formed in the floating diffusion in the output amplifier of FIG. 1,respectively;

FIG. 14 is a partial plan view of an array of offset pixels and colorfilter segments in the solid state imaging device of FIG. 1;

FIGS. 15 and 16 are timing charts showing re-arraying of signal chargesof the first and second fields during the horizontal blanking period inconnection with horizontal transfer of the device of FIG. 14,respectively;

FIG. 17 is a timing chart showing the relationship of the drive signalssupplied for the first field and the output signals in connection withhorizontal transfer of the device;

FIG. 18 is a timing chart showing the relationship of low-speed readoutdrive signals ad output signal in the horizontal transfer of the device;

FIG. 19 is a schematic block diagram showing a three-line readout solidstate imaging device applied to the imaging unit of FIG. 2;

FIG. 20 is a timing chart showing the relationship between the drivesignals and the output signals as applied to the horizontal transfer forthe device of FIG. 19;

FIG. 21 is a schematic block diagram showing a four-line readout solidstate imaging device applied to the imaging unit of FIG. 2;

FIG. 22 is a timing chart showing the relationship between the drivesignals and the output signals as applied to the horizontal transfer forthe device of FIG. 21;

FIG. 23 is a schematic block diagram showing an alternative embodimentof a solid state imaging apparatus according to the present invention;

FIG. 24 is a timing chart useful for understanding an operationalsequence of horizontal transfer consistent with horizontal timingsignals of the initial driving condition at the time of high speeddriving in the solid state imaging device of FIG. 1;

FIG. 25 is a timing chart useful for understanding an operationalsequence of horizontal transfer consistent with horizontal timingsignals of the inverted-branching driving condition at the time of highspeed driving in the device of FIG. 1;

FIG. 26 is a timing chart also useful for understanding an operationalsequence of horizontal transfer at the time of low-speed driving in thedevice of FIG. 1;

FIG. 27 schematically shows signal charges being transferred responsiveto the horizontal timing signals of the initial driving condition at thetime of transfer efficiency measurement on the horizontal transfer pathin the device of FIG. 1:

FIG. 28 schematically shows signal charges being transferred responsiveto the horizontal timing signals of the inverted-branching drivingcondition at the time of transfer efficiency measurement on thehorizontal transfer path in the device of FIG. 1;

FIG. 29 is a graph showing the relationship between the quantity ofresidual transfer charges and the quantity of reference signals on twobranching transfer paths in the device of FIG. 1:

FIG. 30 is a graph showing the relationship between the transferefficiency and the quantity of the reference signals;

FIG. 31 is a timing chart useful for understanding the operationalsequence of mixing of horizontal pixels on a horizontal transfer pathbefore branching in the device of FIG. 1;

FIGS. 32A through 32I showing how the potential level changes which isformed in the respective transfer elements by horizontal pixel mixing onthe horizontal transfer path before branching in the device of FIG. 1;

FIGS. 33 and 34 are block diagrams schematically showing changes in theoutput destination, consistent with the transfer efficiency on thebranching horizontal transfer paths in the device of FIG. 1;

FIG. 35 schematically shows horizontal transfer paths in the device ofFIG. 1, looked from above;

FIG. 36, parts (A) and (B) are a schematic plan view and a schematiccross-sectional view of one of the horizontal transfer paths shown inFIG. 35, respectively;

FIG. 37, parts (A) and (B) are a schematic plan view and a schematiccross-sectional view of the other of the horizontal transfer paths shownin FIG. 35, respectively;

FIG. 38 is a timing chart showing the timing of drive signals suppliedto the respective electrodes shown in FIG. 35;

FIG. 39 is a schematic potential diagram showing the state of transferof signal charges on the horizontal transfer path in FIG. 36;

FIG. 40 is a schematic potential diagram showing the state of transferof signal charges on the horizontal transfer path in FIG. 37;

FIGS. 41A to 41E schematically show the state of transfer of signalcharges on the horizontal transfer path in FIG. 35;

FIG. 42 is a schematic timing chart showing an example of the timing ofdrive signals supplied to the respective electrodes shown in FIG. 35;

FIG. 43 is a schematic timing chart showing another example of thetiming of drive signals supplied to the respective electrodes shown inFIG. 35;

FIG. 44 is a flowchart useful for understanding illustrative processingfor calculating the transfer efficiency;

FIGS. 45 and 46 schematically show illustrative processing forcalculating the transfer efficiency on one and the other of thehorizontal transfer paths, respectively;

FIG. 47 is a graph schematically showing the residual charge quantitiesdetected from one reference signal to another;

FIG. 48 is a graph schematically showing the transfer efficiencycalculated from the residual signal quantities shown in FIG. 47;

FIG. 49 is a flowchart showing illustrative processing of calculatingthe transfer efficiency by the processing sequence shown in FIG. 44 andfor setting a variable value of the duty cycle using the transferefficiency calculated;

FIG. 50 is a block diagram schematically showing a further alternativeembodiment of a digital camera employing the device of FIG. 1;

FIG. 51 is a plan view looked from above, showing a horizontal transferpath in the device of FIG. 1;

FIG. 52 is a partial cross-sectional view showing essential part of ahorizontal transfer path of FIG. 51;

FIG. 53 is a partial plan view of an array of offset pixels and colorfilter segments as applied to the device of FIG. 1;

FIGS. 54A through 54E and 55A through 55E schematically show transfer ofsignal charges R and B, and signal charges G on the horizontal transferpath of FIG. 1, respectively;

FIG. 56 is a timing chart showing the supply timing of drive signal tothe electrode of FIG. 51;

FIGS. 57A through 61B schematically show the potential levels generatedon the horizontal transfer path when the drive signal shown in FIG. 56is applied;

FIG. 62 is a timing chart showing the timing of drive signals suppliedto the electrodes of FIG. 55 on transferring the signal charge G;

FIGS. 63A through 64B schematically show the potential level generatedon applying the drive signal shown in FIG. 62;

FIGS. 65 and 66 are timing charts showing drive signals for providingthe same color of the signal charges output from the same outputamplifier in the first and second lines; and

FIGS. 67A to 67E schematically illustrate the transfer of signal chargesG in two horizontal transfer paths.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A solid state imaging device according to the present invention will nowbe described with reference to the accompanying drawings. With referenceto FIG. 1, in a preferred embodiment of a solid state imaging device 44,signal charges of attributes of colors classified by a branching section54 are transferred with a horizontal transfer speed or rate higher thana predetermined transfer speed, on both of the horizontal transfer paths56 and 58, and converted analog voltage signals 82 and 84 are outputsimultaneously. For transfer with a horizontal transfer speed lower thanthe predetermined transfer speed, the converted analog voltage signal 82is output from the selected horizontal transfer path, such as path 56.The output amplifiers 60 and 62 arranged on plural, e.g. two, horizontaltransfer paths 82 and 84 exhibit differential sensitivities for signalcharge detection, depending on the attributes of colors of signalcharges supplied. By outputting the analog voltage signals 82 and 84under this condition, it is possible to modulate the sensitivity of redand blue signals with respect to the green color to suppress unneededgain to suppress noise.

In the present embodiment, the solid state imaging device of the presentinvention is applied to a digital camera 10. The parts or components notdirectly pertinent to understanding the present invention are not shownnor described.

Referring to FIG. 2, the digital camera 10 includes an optical system12, an imaging unit 14, an amplifier power supply 16, a biasing circuit18, drivers 20, a pre-processor 22, a memory 24, a signal processor 26,a system controller 28, an operating unit 30, a timing signal generator32, a media interface (I/F) circuit 34, media 36 and a monitor display38, which are interconnected as illustrated.

The optical system 12 has an automatic focusing (AF) function ofreceiving incident light 40 from a field being imaged to focus an imageof the field on the imaging surface of the imaging unit 14 responsive toan operation from the operating unit 30. The optical system 12 adjuststhe angle of view or focal length, responsive to a zooming operation ora half-stroke depression of a shutter release button, not shown, on theoperating unit 30. The optical system 12 also has the function ofadjusting the diaphragm or iris stop for the incident light 40 to avalue in keeping with the manipulation on the operating unit 30 in theimaging unit 14. The optical system 12 adjusts the incident light 40 toa light beam 42 based on these functions to focus the light beam 42 ontothe imaging unit 14.

The imaging unit 14 includes a solid state imaging device 44, which isimplemented by a charge-coupled device (CCD) shown in FIG. 1 with theillustrative embodiment. The imaging device 44 includes color filtersegments, as shown in FIG. 14, arranged in the incoming direction of theincident light beam 42 according to the mounting positions ofphotosensitive cells. The device 44 has the function of color-separatingthe incident light beam 42, converting the light of the color componentsresulting from the color separation into signal charges byphotosensitive cells 46 and outputting corresponding electrical signals.The device 44 reads out signal charge accumulated in proportion to lightexposure, to a vertical transfer path 48 for transferring sequentiallyin the vertical direction. The device 44 includes a horizontal transferpath 50 extending in a direction substantially perpendicular to thevertical transfer path 48. The signal charges, transmitted vertically,are supplied to the horizontal transfer path 50.

The horizontal transfer path 50 of the present embodiment has its outputend 52 including a branching section 54. From the branching section 54,there are formed horizontal transfer paths 56 and 58 in a branchingfashion. Separate output amplifiers 60 and 62 are provided at outputends of the horizontal transfer paths 56 and 58, respectively. Theoutput amplifiers 60 and 62 are floating diffusion amplifiers having thefunction of converting signal charges into a corresponding analogvoltage signal. To the output amplifiers 60 and 62 are connected powersupply lines 64 and 66, respectively. The power supply lines 64 and 66are connected independently from the power supply 16. The outputamplifiers 60 and 62 are supplied from the drivers 20 with reset signals68 and 70, respectively. The output amplifiers 60 and 62 thus suppliedwith the reset signals may run independently. In the description tofollow, signals are denoted by reference numerals of connection lines onwhich they appear.

The branching section 54 is supplied with a bias signal 72 from thebiasing circuit 18. With the bias signal thus supplied, the signalcharges from the horizontal transfer path 50 are branched to thehorizontal transfer path 56 or 58. A horizontal drive signal 74 issupplied to the horizontal transfer path 50, while a horizontal drivesignal 76 is supplied to each of the horizontal transfer paths 56 and58. The horizontal drive signal 76 has a frequency equal to, forexample, one half the frequency of the horizontal drive signal 74. Bydriving the horizontal transfer paths 56 and 58 in this manner, highspeed readout may be enabled even though the design frequency ranges ofthe output amplifiers 60 and 62 are halved. The device 44 is alsosupplied with an overflow drain (OFD) pulse 78 and with a vertical drivesignal 80.

In this manner, the device 44 outputs two channels of output signals 82and 84 from the output amplifiers 60 and 62, respectively to thepre-processor 22. The horizontal transfer in the device 44 will bedescribed in detail subsequently.

Reverting to FIG. 2, the amplifier power supply 16 has the function ofsupplying the supply power to the output amplifiers 60 and 62 arrangedin the device 44. The amplifier power supply 16 supplies the supplypower depending on whether the device 44 is to supply a one-channeloutput or a two-channel output. This power supply is controlled by acontrol signal 86 supplied from the signal processor 26 to the amplifierpower supply 16.

The biasing circuit 18 has the function of supplying a bias signal 72 tothe branching section 54. The bias signal 72 is applied as a biasvoltage which prescribes the gain. The biasing circuit 18 is controlledby a control signal 88 supplied from the signal processor 26.

The drivers 20 have the function of supplying a variety of drive signalsfor driving the device 44. The drivers 20 are supplied with pluraltiming signals 90 from the timing signal generator 32. The driversinclude an OFD pulse output circuit 92, a vertical (V) driver 94, ahorizontal series (HS) driver 96, a horizontal parallel (HP) driver 98,and a reset (RS) driver 100, as shown in FIG. 3. The OFD pulse outputcircuit 92 outputs an OFD pulse 78 to the device 44. The V driver 94, HSdriver 96 and HP driver 98 output a vertical drive signal 80, thehorizontal drive signal 74 and the horizontal drive signals 76 to thedevice 44, respectively. The horizontal drive signal 76 has a perioddouble that of the horizontal drive signals 74. The RS driver 100outputs the reset signals 68, 70 to the device 44.

Reverting to FIG. 2, the pre-processor 22 has an analog front-end (AFE)function. This function removes the noise by correlated double sampling(CDS) for the analog electrical signals 82, 84 supplied, whiledigitizing the noise-free analog electrical signals by analog-to-digital(A/D) conversion. The pre-processor 22 is supplied from the timingsignal generator 32 with a timing signal or with sampling signals 106and 108 for performing pre-processing on the input signals of respectivechannels for noise removal and A/D conversion. It is noted that twochannels of analog electrical signals 82 and 84 are supplied to thepre-processor 22. In case only one of the two channels is supplied withan input, and one of the sampling signals 106 and 108 for the inputchannel is supplied for the sole channel thus receiving the input, itmay be sufficient to activate only one channel of the operation of theCDS sampling and A/D conversion, thereby reducing power consumption. Thepre-processor 22 is responsive to the supply of the sampling signals 106and 108 to output one or two of channels of digital signals 110 and 112to the memory 24.

The memory 24 has the function of temporarily storing the digitalsignals 110 and 112 supplied and outputting the stored signals.Specifically, a line memory is provided for each channel in the memory24. The memory 24 has its input and output controlled by a controlsignal 116 supplied over a bus 114. The memory 24 is responsive to thecontrol signal 116 to output the input digital signals 110 and 112 as adigital signal 118 over the bus 114 and signal line 120 to the signalprocessor 26.

The signal processor 26 has the function of processing the digitalsignal 118 supplied to generate a control signal. The signal processor26 includes a power supply control 122, a gain control 124, an AFcontrol 126, an automatic exposure (AE) control 128, an automatic whitebalance (AWB) control 130 and an data converter 132. The power supplycontrol 122 has the function of generating a control signal 86 dependingon high speed readout or low speed readout, based on, for example, scenediscrimination in the system controller 28. The power supply control 122outputs the generated control signal 86 to the power supply 16.

The gain control 124 has the function of generating a control signal 88depending on which of the horizontal transfer paths 56 and 58 the signalcharge from the horizontal transfer path 50 via the branching section 54are to be supplied to. The gain control 124 outputs the control signal88 to the bias control 18. The bias control 18 routes the bias signal 72to the branching section 54. The AF control 126 has the function ofadjusting the focus based on produced image data. The AE control 128 hasthe function of finding an evaluation value based on the produced imagedata, for adjusting the diaphragm and the shutter speed. The AF control126 and the AE control 128 are responsive to adjustment to transmit acontrol signal, not shown, over signal line 120, bus 114 and signal line134 to the system controller 28. The AWB control 130 has the function ofadjusting the white balance based on produced image data. The dataconverter 132 has the function of converting the image data, obtained onhigh-speed readout as two-channel data, into, e.g. dot sequential imagedata corresponding to the array of the color filter segments, andforming one frame of image. In case the output from the pre-processor 22is obtained by low speed readout, the data converter 132 is to cope withone-channel output, and accordingly performs the positional conversionfor a one-channel output.

The signal processor 26 also has the function, not shown, ofsimultaneously outputting the three-color data supplied, and using theimage data of the three primary colors obtained simultaneously toproduce luminance/chrominance (Y/C) signals, which is sometimes referredto as synchronization. The signal processor 26 also has the function ofconverting the produced Y/C signals into displayable signals, such assignals appropriate for a liquid crystal display monitor. The signalprocessor 26 also has the function of compressing the Y/C signalsproduced, depending on the recording modes, and decompressing thecompressed signals for restoring and reproducing the image data. Therecording modes may be exemplified by JPEG (Joint Photographic ExpertsGroup), MPEG (Moving Picture Experts Group) and raw data modes. Thesignal processor 26 transmits the image data processed in accordancewith the recording modes over a signal line 120, a bus 114 and a signalline 136 to the media I/F circuit 34. The signal processor 26 alsooutputs a liquid crystal monitor signal 138 to the monitor display 38.

The system controller 28 has the function of generating a variety ofcontrol signals responsive to an operating signal 140 from the operatingunit 30, as later described. The system controller 28 includes a settingand operational control functional unit, not shown. This setting andoperational control functional unit receives the control signal 140 fromthe operating unit 30 as a setting condition to generate a controlsignal 142 depending on the setting condition. The setting andoperational control functional unit generates the control signal 142which controls whether an output of horizontal transfer is to cause adouble output or a single output. Thus, the system controller 28verifies whether or not the horizontal transfer is adapted for highspeed readout, depending on moving picture mode setting, speed settingof repeated shooting, scene decision and a depressing operation for ashutter release button, not shown. The system controller 28 then outputsthe control signal 142 generated to the timing signal generator 32. Inaddition, the system controller 28 controls the memory 24, the signalprocessor 26 and the media I/F circuit 34.

The operating unit 30 includes a power supply switch, a zoom button, amenu display selector switch, a select key, a moving picture modesetting unit, a repeated shooting speed setting unit and a shutterrelease button which are not shown. The power supply switch is used forturning on or off the power supply of the digital camera 10. The zoombutton controls the angle of view of the field being imaged, inclusiveof a subject being imaged, and adjusts the focal length of the subjectresponsive to the control. The menu display selector switch is used forselecting the menu displayed on the liquid crystal monitor display tocause movement of a select cursor, and may, for example, be a crossswitch. The selector key is used for selecting the items of the menudisplayed.

The moving picture setting unit sets whether or not a moving picture isto be displayed on the liquid crystal monitor display, using, e.g. aflag. By this setting, the digital camera 10 displays an image of thefield captured on the monitor display 38 in the form of through-image.The moving picture setting unit includes items for setting theresolution, the number of displayed frames and the repeated shootingspeeds. The items for resolution are those for selecting the resolutionof, for example, HDTV (High-Definition Television) standard/thereference VGA (Video Graphics Array). The number of displayed frames isan item for selecting one of 30 and 15 (30/15).

The repeated shooting speed setting unit sets the speed in repeatedshooting from plural repeated shooting speeds as set. It sets the speedin repeated shooting depending on two inputs/one input. The number oftimes of repeated shooting is set for an image with a predeterminednumber of pixels. One input or two inputs is selected, respectively, indriving the solid-state imaging device, depending on that the number oftimes of repeated shooting is less, or equal to or greater than athreshold value of the number.

The shutter release button has the function of selecting the operationaltiming or the operational mode of the digital camera 10 responsive tohalf-stroke/full-stroke depressions. The shutter release buttoninitiates the AE and AF operations responsive to the half-strokedepression. The AE and AF operations use an image obtained on movingpicture display to find out a diaphragm, a shutter speed and a focallength which may be optimum. The shutter release button also sends therecording start/recording end timing to the system controller 28, as anoperating signal 140, by the full-stroke depression, to define anoperational timing responsive to the setting mode of the digital camera10. The setting modes may be exemplified by, for example, a still imagerecording mode and a moving picture recording mode.

The timing signal generator 32 has the function of generating a varietyof timing signals for the device 44 of the imaging unit 14. These timingsignals may be exemplified by vertical and horizontal synchronoussignals, field shift gate signals, vertical and horizontal timingsignals, OFD pulse signals and reset signals. This function generates avariety of timing signals 90, 106 and 108 responsive to the controlsignal 142 from the system controller 28. The timing signal generator 32outputs a variety of the timing signals 90 to the drivers 20. The timingsignal generator 32 has the function of generating a reference clocksignal and, in particular, generates the horizontal timing signal. Thetiming signal generator 32 frequency-divides the horizontal timingsignal to generate two horizontal timing signals of frequenciesdifferent from each other. The timing signal generator 32 is responsiveto the control signal 142 from the system controller 28 to output one ofthe sampling signals 106 and 108 as one-channel output. In this manner,it is possible to suppress power consumption of the digital camera 10.

The media I/F circuit 34 has the interface control function ofcontrolling the recording and/or reproduction of image data depending onthe recording media which may be in use. The media I/F circuit 34 isable to control recording/readout of image data 144 for a PC (PersonalComputer) card as a semiconductor recording medium. The media I/Fcircuit 34 is also able to control recording/readout of image data 136supplied over bus 114 under control by an enclosed USB (Universal SerialBus) controller. There are a variety of standards for the semiconductormemory cards used for the recording media 36.

For the monitor display 38, a liquid crystal monitor display, forexample, may be used. The image data 138 supplied from the signalprocessor 26 is displayed on the monitor display 38.

With the above-described configuration, the digital camera 10 may be runsatisfactorily as signal charges from the horizontal transfer path 50are read out as two inputs at a high speed or as one output at a lowspeed.

The electrode structure in which the horizontal transfer path 50 isbifurcated at the branching section 54 into the horizontal transferpaths 56 and 58, and the transfer of signal charge responsive to a drivesignal, will now be described. For facility in description, the side ofthe horizontal transfer path 56 and that of the horizontal transfer path58 are separately described. For each of the horizontal transfer paths50, 56 and 58, each transfer element is formed by paired two electrodesof polycrystalline silicon (polysilicon) and paired two impurity layersin the vicinity of a silicon substrate. A stepped potential gradient isformed by applying a drive signal of the same potential to the twoelectrodes.

From the right-hand side towards an electrode HSL of the branchingsection 54, there are sequentially formed polysilicon electrodes HS4,HS3, HS4, HS1, HS2, HS3, HS2 and HS1 on the horizontal transfer path 50with each polysilicon electrode being formed by an electrode pair.Referring to FIG. 4, four polysilicon electrodes HP1, HP2, HP1 and HP2,and an OG (Output Gate) electrode are formed from the electrode HSL ofthe branching section 54 towards an output amplifier 60. Adjacent to theleft side of the OG electrode, there is formed a floating diffusion (FD)layer. Adjacent to the left end of the FD layer is formed a resetelectrode (RS). Ultimately, next to the left end of the reset electrodeis formed a reset drain (RD) layer.

Next, the above electrodes are imaginarily sectioned, beginning from thereset drain RD on the left end to the electrode HP1 on the horizontaltransfer path 56 and further from the branching section 54 to theelectrode HS2 on the horizontal transfer path 50 for illustrating thesectioned surfaces as shown by a chain-dotted line IV-IV. As may be seenfrom these sectioned surfaces, an impurity layer is formed directlybelow each electrode on a P-type substrate not shown. A plural number ofthe impurity layers are formed in register with the respectiveelectrodes. For generating the respective impurity layers, impuritiesare doped by using, e.g. an ion implantation method. The sorts and theconcentrations of the impurities doped characterize the magnitudes ofthe potential gradients. The potential gradients of preset magnitudesare determined in dependence upon the voltage level of the drive signalsapplied to the electrodes formed directly on the top of the impuritylayers.

A variety of drive signals supplied to the respective electrodes willnow be described. A drive signal φHS2 is supplied to the electrode HS2.A drive signal φHSL is supplied to the electrode HSL. The drive signalφHSL is a constant bias voltage. Drive signals φHP1 and φHP2 aresupplied to the electrodes HP1 and HP2, respectively. Drive signals φOG,φRS and φRD are supplied to the electrodes OG, RS and the reset drainRD, respectively.

FIG. 5 shows the timing for these drive signals. As regards the phase ofeach of the drive signals, the drive signals φHS1 and φHS3 of FIG. 5,part (A), are two phase drive signals phase-reversed by 180° from thedrive signals φHS2 and φHS4 shown in part (B). The drive signal φHP1 ofpart (C) and the drive signal φHP2 of part (D) are phase-reversed fromeach other and are each a two-phase drive signal.

Turning to the period of the drive signal, the drive signals of the setsof FIG. 5, parts (A) and (B), are of the period one-half that of thedrive signals of the sets of parts (C) and (D). That is, frequency ofthe drive signals of the sets of parts (A) and (B) is twice that of thedrive signals of the sets of parts (C) and (D). The drive signal φRSsupplies a level “H” at timings of, e.g. t=1, t=5, . . . , that is, attiming of t=4n+1, where n is a variable inclusive of zero. Outputsignals OS1 and OS2 are supplied as indicated in part (F).

Reverting to FIG. 4, since the drive signal φHSL is supplied in a mannernot shown, there are generated, in a region directly below the electrodeHSL supplied with the drive signal φHSL, a potential level of aperpetually fixed reference level 146 and a potential level or barrier148 prohibiting reverse flow of signal charges supplied from thehorizontal transfer path 50.

The potential generated responsive to the drive signals supplied, andthe movement of signal charges accompanying the potential generationwill now be described. Signal charges having attributes of colors red(R), green (G) and blue (B) are termed signal charge R, G and B,respectively. Referring to FIG. 5, part (B), the drive signal φHS2 is ata level “L”, and the drive signals φHSL and φHSP1 are supplied. Thedrive signal φHS1 is at a level “L”. When the drive signals are suppliedin this manner, the signal charge R is retained in the branching section54. The level “L” is supplied at this time to the impurity layer of theelectrode HP1, not shown, adjacent to the electrode HSL, so that thereis generated a potential or a barrier which is just high enough toprohibit, for example, the signal charge R from mixing into thehorizontal transfer path 56, as indicated by a broken line 150.

The drive signal φHP2 of the level “H” is supplied to the otherelectrode HP2 neighboring to the branching section 54. This generates apotential level 152 lower than the reference level to permit the signalcharge R to flow into the horizontal transfer path 58. At this time, thesignal charge R is present in both packets of the reference level 146and the potential level 152.

There are formed impurity layers 154 and 156 directly underneath theelectrodes HP2 and HP1. When the level “H” is supplied, there aregenerated stepped potential levels composed of a level lower than thereference level 146 and the lowest level. When the level “L” issupplied, there are generated stepped potentials composed of a levelhigher than the reference level 146 and the same level as the referencelevel 146. Hence, the potential generated becomes sequentially lower ina stepped fashion along the transfer direction of the signal charges. Ata timing t=1, signal charges G are stored at every second electrodes onthe horizontal transfer path 56.

At the next timing t=2, the drive signal φHS2 at a level “H” is appliedto the electrode HS2 as shown in FIG. 5, part (B). This causes theimpurity layers of the electrode HS2 to generate a potential level 148and the reference level 146. This allows the electrode HS2 to generate apacket between it and the electrode HSL. This packet holds the signalcharge G. The rear side electrodes are supplied with the drive signalsof the same level as at the timing t=1. Hence, the potential levels arethe same as those at timing t1. In the interim, the signal charge R atthe electrode HSL is moved to the electrode HP2 on the horizontaltransfer path 58 on a lower side not shown, on the figure sheet. Thesignal charge R in this state is indicated by a broken line.

At the next timing t3, the drive signal φHS2 of the level “L” is appliedto the electrode HS2 as shown in FIG. 6. This sets the potential levelsat the timing t1. The signal charge G held in the packet generated atthe timing t=2 is moved to the reference level 146 at the branchingsection 54. At this time, the drive signal φHP1 of the level “H” issupplied to the electrode HP1 of the horizontal transfer path 56neighboring to the electrode HSL. The potential generated in theimpurity layer associated with the electrode HP1 is higher in level thanthe reference level 146, as indicated by a broken line 158. As a result,the signal charge G is present in both packets of the reference level146 and the potential level 160. At this time, the drive signal φHP2 ofthe level “L” is supplied to the electrode HP2 of the horizontaltransfer path 58. This generates the potential level of a broken line158 in the electrode HP2. This potential level prohibits the signalcharge G from mixing into the horizontal transfer path 58. The signalcharge G at the branching section 54 is moved to the packet formed atthe electrode HP1 on the horizontal transfer path 56 on an upper part ofthe drawing sheet.

The drive signal φHP2 of the level “L” is applied to the electrode HP2neighboring to the electrode HP1. This generates the potential level 148and the reference level 146 in the impurity layers 154, 156,respectively. The drive signal φHP1 of the level “H” is applied to theelectrode HP1 neighboring to the electrode HP2. This generates a levellower than the reference level 146 and the lowest potential level in theimpurity layers 154 and 156, respectively. The potential level 148 andthe reference level 146 are generated by the level “L” supplied to theneighboring electrode HP2. As a result, the signal charge G held in thepacket at t=2 is moved to and retained in the packet generated in theelectrode HP1.

The signal charge G, retained in the packet, generated at the timingt=2, is moved towards the output side, and thence transferred viaelectrode OG because of the increment of the potential level.

Next, at a time t=4, the drive signal φHS2 of level “H” is supplied tothe electrode HS2, so that, at this electrode, the potential which isthe same as that at time t=2 is generated. The signal charge B isretained in the packet generated at this time. The signal charge G atthe branching section 54 is moved to the packet formed directlyunderneath the electrode HP1 on the horizontal transfer path 56. A drivesignal of the same level as that at time t=3 is supplied to all of rearside electrodes. Hence, the potential levels generated are the same asthose at time t=3.

Next at time t=5, the impurity layers in register with the electrode HS2generate the same potential levels as at time t=1. This generates apotential level 158, directly underneath the electrode HP1, neighboringto the branching section 54, thus providing a potential barrier againstthe signal charge B. The signal charge B may be made not to becolor-mixed into the horizontal transfer path 56. The branching section54 causes the incoming signal charge B to be moved further to thehorizontal transfer path 58. The horizontal transfer path 56 is suppliedwith the drive signals which are of the same level as at time t=1.Hence, the potential levels generated are the same as that at time t=1.At time t=4, the signal charge G supplied to the FD layer is convertedinto an analog voltage signal which is output to the output amplifier60.

Next, the above electrodes are imaginarily sectioned, beginning from thereset drain RD on the left end to the electrode HP2 on the horizontaltransfer path 58 and further from the branching section 54 to theelectrode HS2 on the horizontal transfer path 50, for illustrating thesectioned surfaces. As may be seen from these sectioned surfaces, animpurity layer is formed directly underneath each electrode on a P-typesilicon substrate. The P-type silicon substrate is not shown. A pluralnumber of the impurity layers are formed in register with the respectiveelectrodes. In generating the impurity layers, the concentration of eachof the impurity layers is adjusted to generate preset potential levelsdepending on the voltage levels of the drive signals. The horizontaltransfer path 58 is featured by having one more electrodes than thehorizontal transfer path 56.

At time t=1, the drive signal (φHS2 of the level “H”, the drive signalφHSL of the constant bias voltage and the drive signal φHP1 of the level“L” are supplied to the electrodes of the horizontal transfer path 58,as shown in FIG. 5, part (B). When the drive signals are applied in thismanner, a signal charge R is retained in the branching section 54. Atthis time, the potential level generated by the impurity layer of theelectrode HP2, not shown, adjacent to the electrode HSL, on applying thedrive signal φHP2, is lower by one step than the reference level 146.The potential level 150 generated directly underneath the electrode HP1on the horizontal transfer path 56, operates as a potential barrier, andprevents mixing of the signal charge R.

A sum total of four electrodes, that is, the electrodes HP1 and HP2 areprovided next to the electrode HP2. Hence, the number of the electrodesprovided on the horizontal transfer path 58 is one more than that on thehorizontal transfer path 56. The impurity layers 154 and 156 of FIG. 4,for example, are sequentially provided, when looking from the rightside, as the impurity layers lying directly underneath the fourelectrodes. Since the drive signal φHP1 of the level “L” is supplied tothe electrode HP1, the potential level 148 and the reference level 146are formed directly underneath the electrode HP1. The drive signal φHP2of the level “H” is supplied to the electrode HP2. This generates thelevel by one step lower than the reference level 146 and the lowestpotential level directly underneath the electrode HP2.

At time t=1, the drive signals are supplied as described above, andhence a packet is generated directly underneath the electrode HP2. Thesignal charge R and G are retained in packets sequentially from thebranching section 54.

Next, at time t=2, the drive signal φHS2 of the level “H” is applied tothe electrode HS2 as shown in FIG. 5, part (B). This causes the impuritylayers of the electrode HS2 to generate potential levels which are ofthe same level as that at time t=2 of FIG. 4 to generate a packet. Thesignal charge G is retained in this packet. From this time on, the drivesignals of the same level as at time t=1 are supplied to the electrodesof the horizontal transfer path 58. Hence, the potential levelsgenerated are the same as those at time t=1.

The potential levels at t=3 are shown in FIG. 8, part (B). At time t=3,the drive signal φHS2 is applied at level “L” to the electrode HS2. Thissets the potential levels which are the same as those at time t=1. Thesignal charge G retained in the packet directly below the electrode HS2at time t=2 is moved to the branching section 54 of the reference level146. At this time, the drive signal φHP2 is applied at level “L” to theelectrode HP2 on the horizontal transfer path 58 neighboring to theelectrode HSL. The potential level for the electrode HP2 is slightlyhigher than the reference level 146 as indicated by broken line 158, dueto the impurity layer associated with the electrode HP2 which is notshown because of cross-section. That is a potential barrier is formed toprevent the mixing of the signal charges G into the horizontal transferpath 58. On the other hand, the potential indicated by a broken line 160is formed by the potential level “H” supplied to the electrode HP1 ofthe horizontal transfer path 56. This causes movement of the signalcharge G along the direction perpendicular to and into the drawingsheet, as indicated by arrow 162. There is generated a packet by thepotential 160 directly underneath the electrode HP1 supplied with thedrive signal φHP1 on the horizontal transfer path 56 as indicated attime t=1 in FIG. 4.

On the horizontal transfer path 58, the packet generated on theelectrode HP2 at time t=2 is formed on the electrode HP1, responsive tothe supply of the level “H” of the drive signal φHP1. The signal chargesR and B are retained in the packets of the electrodes HP1 sequentiallyfrom the branching section 54. The signal charge R on the electrode HP2,retained in the packet, generated at time t=2 is shifted towards theoutput with rise in the potential level, and transferred to the FD layervia the electrode OG.

Next at time t=4, there are generated the same potential levels as thoseat time t=2. The signal charge B is retained in a packet then generated.The drive signals of the same levels as those at time t=3 are suppliedto the rear side electrodes. Hence, the potential levels generated arethe same as those at time t=3. The potential level directly underneaththe electrode HP2 neighboring to the electrode HSL is higher than thereference level 146 as indicated by a broken line 158. On the otherhand, the potential level formed directly underneath the electrode HP1neighboring to the electrode HSL is lower than the reference level 146as indicated by a broken line 160.

Then, at time t=5, the same potential level as that at time t=1 isgenerated. The signal charges R and B are retained in the packets of theelectrode HP2 sequentially from the branching section 54. At time t=4,the signal charge R supplied to the FD layer is converted into an analogvoltage signal which is output from the output amplifier 60.

The operating principle of horizontal transfer responsive to supply ofdrive signals is shown in FIGS. 9A to 9E. In horizontal transfer, thesignal charges R_G1_B_G2 supplied at time t=1 from the horizontaltransfer path 50 to the branching section 54 are distributed at thebranching section 54 to the horizontal transfer paths 56 and 58. Thesymbol _ denotes a potential barrier region. It may be seen that, on thehorizontal transfer path of FIG. 9, the potential barrier separating thesignal charge is generated for the length of one electrode. Thehorizontal transfer path 56 transfers only the signal charges Gresponsive to the drive signals supplied. At the above time point, thepotential barrier is formed at the electrode HP1 of the horizontaltransfer path 56 neighboring to the branching section 54 to prevent thesignal charge R from being mixed into the horizontal transfer path 56.The horizontal transfer path 58 transfers the signal charge R and Bresponsive to the drive signals supplied.

The horizontal transfer path 50 is operated at a frequency double thatof the horizontal transfer paths 56 and 58. Thus, at time t=2, thehorizontal transfer path 50 horizontally transfers one packet of thesignal charge it holds, towards the branching section 54, responsive tothe drive signals supplied. Conversely, on the horizontal transfer paths56, 58, there is no change in the transfer of signal charges, becausethe drive signals undergo no level changes. However, the signal charge Rin the branching section 54 is moved to a packet generated in theelectrode HP2, because the potential level at the electrode HP2 is lowerthan the reference level 146.

At time t=3, the horizontal transfer path 50 horizontally transfers thesignal charges it holds, by one packet each towards the branchingsection 54. A signal charge G1 is retained in the packet generateddirectly underneath the branching section 54 and the electrode HP1 ofthe horizontal transfer path 56 neighboring to the branching section 54.At this time point, there is generated a potential barrier in theelectrode HP2 on the horizontal transfer path 58 neighboring to thebranching section 54 to prohibit the signal charge G1 from mixing intothe horizontal transfer path 58. The horizontal transfer paths 56 and 58horizontally transfer the signal charge it holds, towards the outputamplifiers 60 and 62 on the packet-by-packet basis. This transfers thesignal charge G and B to the FD layers of the output amplifiers 60 and62 on the horizontal transfer paths 56 and 58.

Then, at time t=4, the horizontal transfer path 50 horizontallytransfers the signal charges it holds, towards the branching section 54by one packet. The signal charge G₁ is moved to a packet directlyunderneath the electrode HP1 of the horizontal transfer path 56neighboring to the branching section 54. The signal charge R is moved toa packet directly underneath the electrode HP1 of the horizontaltransfer path 58 neighboring to the branching section 54.

At time t=5, the horizontal transfer paths 50, 56 and 58 horizontallytransfer the signal charges by one packet towards the output side. Thus,the output amplifiers 60, 62 simultaneously convert the signal chargesof the colors G and B into analog voltage signals, which are then outputas output signals OS1 and OS2. This eliminates difference generated inthe processing of the output signals OS1 and OS2 with lapse of time.

Meanwhile, if the difference in the processing with lapse of time istolerable, the output signals OS1 and OS2 may be output alternately.

By the above sequence of operations, it is possible to classify signalcharges having color attributes to transfer and output the signalcharges without color mixing. In general, it is required of the solidstate imaging device to read out signal charge generated, at a highspeed in order to cope with the increasing number of pixels. This demandaffects the frequency band in the output amplifiers on the horizontaltransfer path. The solid state imaging device is difficult to drive at afrequency higher than a preset frequency due to shortage in thefrequency band. However, with the device 44 of the instant embodiment,it is possible to read out output signal charges from color to colorwithin a preset frequency band by bifurcating an output and increasingthe number of output channels even though the driving frequency of thehorizontal transfer path 50 is increased in order to cope with theincreasing number of pixels. That is, an improved signal charge readoutspeed may be achieved.

The sensitivity of charge detection in the output amplifiers 60 and 62will now be described. The output amplifier is divided into a floatingdiffusion section FD and an amplifier section. The sensitivity of chargedetection basically depends on the parasitic capacitance C_(fd) of thefloating diffusion section FD. This parasitic capacitance C_(fd) in turndepends on the sum of five capacitances. These five capacitances are thePN (Positive-Negative) junction capacitance C_(sub) between the floatingdiffusion section FD and the substrate, the parasitic capacitance C_(o)with the output gate OG terminal, the capacitance of the reset RSterminal C_(r), the gate-drain capacitance C_(d) of an MOS (Metal OxideSemiconductor) transistor in an output amplifier connected to thesection FD as a source follower amplifier, and a gate-to-sourcecapacitance C_(s) of the MOS transistor.

It is noted that the gate-to-source capacitance C_(s) appears to besmaller due to the source follower gain G. Thus, the parasiticcapacitance C_(fd) may be expressed byC_(fd)=C_(sub)+C_(o)+C_(r)+C_(d)+C_(s) (1−G).

If desired to provide a difference in sensitivity in charge detection ofthe output amplifiers 60 and 62, several conditions are involved. Thefirst condition is to provide a difference in the gate capacitances ofthe output amplifiers. For providing the difference in the gatecapacitances, the difference in the sensitivity is varied mainly by thegate-drain capacitance C_(d). The channel widths and channel lengths inthe MOS transistors of the output amplifiers 60 and 62 are W, w, L andl, respectively, as shown in FIGS. 10A and 10B. Neither the ratio of thechannel width to the channel length W/L of the MOS transistor shown inFIG. 10A nor the ratio of the channel width to the channel length w/l ofthe MOS transistor shown in FIG. 10B is changed. By so setting, thefrequency response or the gain G is not changed appreciably. However,the gate capacitance may be varied significantly. By this variation, thedifference in sensitivity in charge detection may be afforded to theoutput amplifiers 60 and 62. That is, the output amplifier 60 may havelow sensitivity in charge detection, while the output amplifier 62 mayhave high sensitivity in charge detection.

The second condition is providing a difference in thickness of a siliconnitride film (SiN) 166 formed on an N⁺ layer 164 in the floatingdiffusion section (FD). The thickness of the nitride film 166 gives riseto the connection capacitance of the nitride film 166 and the N⁺ layer164, in a manner different from the PN junction capacitance Csub. If thethickness of the nitride film 164 is thicker than the nitride film 168of FIG. 11B, the junction capacitance is increased. The difference insensitivity in charge detection may be afforded to the output amplifiers60 and 62 by taking advantage of this feature. That is, the outputamplifier 60 is lowered in sensitivity in charge detection, while theoutput amplifier 62 is raised in sensitivity in charge detection.

The surface area in the floating diffusion section FD represents a thirdcondition in mainly varying the PN junction capacitance C_(sub). Thisthird condition takes advantage of the fact that the surface of the PNjunction is proportional to parasitic capacitance. The output amplifier60 may be decreased in sensitivity in charge detection in proportion tothe increase in a surface area 170 of the nitride film as shown in FIG.12A, while the output amplifier 62 may be increased in sensitivity incharge detection in proportion to the decrease in a surface area 170 ofthe nitride film as shown in FIG. 12B.

In addition, a fourth condition is provided as a special condition ofthe second condition in prescribing the junction capacitance between thenitride film 166 and the N⁺ layer 164. The fourth condition is thepresence or absence of the nitride film. With the output amplifier 60,the sensitivity in charge detection is increased by forming the nitridefilm 166 for the floating diffusion section FD based on this conditionas shown in FIG. 13A. With the output amplifier 62, the sensitivity incharge detection is decreased by not forming the nitride film 166 forthe floating diffusion section FD, that is, by forming only the N⁺ layer164 as shown in FIG. 13B.

The imaging device 44 of the present embodiment is of a so-calledhoneycomb array. More specifically with reference to FIG. 14, thephotosensitive cells 46 are arrayed in the same row direction at a pitchPP and in the same column direction at the same pitch PP, while thephotosensitive cells 46 of a row or a column neighboring to a given rowand a given column of the photosensitive cells 46, respectively arearrayed with a shift of one-half pitch in both the row and columndirections. A color filter formed on the incident light side of thephotosensitive cells 46 is of three primary colors R, G and B, andconstituted by plural color segments R, G and B. The color segments Gare arrayed in a square pattern, while the color segments R and B arearrayed in a complete RB checkered pattern. That is, the filter array isa so-called G-square RB-checkered pattern. With the pixels orphotosensitive cells 46 arrayed with offset as described above, a pluralnumber of the vertical transfer paths 48 are formed meandering such asbypassing the pixels.

The signal charges as read out are transferred on the vertical transferpaths 48 towards the horizontal transfer path 50 not shown in FIG. 14,responsive to eight-phase drive signals φV1B, φV2, φV3B and φV4 to φV8.The signal charges are transferred towards the horizontal transfer path50 by using line memory LM. Although not shown in FIG. 14, electrodesHS1, HS2, HS3, HS2, HS1, HS4, HS3 and HS4, . . . are provided on thehorizontal transfer path 50, when looking from its left end. With thehoneycomb array and the G-square RB checkered pattern, signal charge arere-arrayed or re-positioned in an output sequence by taking advantage ofthe line memory LM.

This re-arraying may be achieved using a drive signal φLM in FIG. 15,part (A), supplied to the line memory LM and drive signals φHS1 to φHS4in parts (B) to (E), supplied to the electrodes of the horizontaltransfer path 50. For this re-arraying, the drive signals φHP1 and φHP2not temporally changed in level, as shown in FIG. 15, parts (F) and (G),and FIG. 16, parts (F) and (G) are supplied to the horizontal transferpaths 56 and 58. This does not activate the horizontal transfer paths 56and 58.

The timing chart of FIG. 15 shows re-arraying or re-positioning of thefirst field during the horizontal blanking (HBL) period. Initially, thedrive signal φLM of FIG. 15, part (A), becomes “L” in level at time 174.At this time, only drive signal φHS2 of part (C) is at the level “H”.Signal charges are transferred from the line memory LM to the packetgenerated directly underneath the electrode HS2 of the horizontaltransfer path 50 supplied with the drive signal φHS2.

The drive signal φHS1 of FIG. 15, part (B), supplied to the electrodeHS1, then goes “H” in level. This generates a packet directly underneaththe electrode HS1 to cause movement of the signal charge. The drivesignal φHS4 of part (E), supplied to the electrode HS4, then goes “H” inlevel. This generates a packet directly underneath the electrode HS4 tocause movement of the signal charge. The drive signal φHS3 of part (D),supplied to the electrode HS3, then goes “H” in level. This generates apacket directly underneath the electrode HS3 to cause movement of thesignal charge. The drive signal φLM of part (A) goes “L” at time 176.Only the drive signal φHS1 of part (B) goes “H” in level. The signalcharge are supplied to and retained in this manner in the packet.

The timing chart of FIG. 16 shows re-arraying of the second field duringthe horizontal blanking (HBL) period. Initially, the drive signal φLM ofFIG. 16(A) goes “L” at time 178. Only the drive signal φHS4 of FIG. 16,part (E) is “H” in level. The signal charges are supplied from the linememory LM to a packet generated directly underneath the electrode HS4 onthe horizontal transfer path 50 supplied with the drive signal φHS4. Thelevel “H” is then supplied in the sequence of parts (B), (C), (D), (C)and (B), depending on the electrode array. This causes movement of thesignal charge with the movement of the packet generated. That is, thefirst signal charge is sequentially moved in the sequence of theelectrodes HS4, HS1, HS2, HS3, HS2 and HS1. The first signal charge istransiently retained in the electrode HS1.

The drive signal φLM of FIG. 16, part (A), becomes “L” in level at time180. At this time, only the drive signal φHS3 of part (E) is at a level“H”. The second signal charge is transferred from the line memory LM tothe packet generated directly underneath the electrode HS3 on thehorizontal transfer path 50 supplied with the drive signal φHS3. Thelevel “H” then is supplied in the order of parts (C) and (B) dependingon the electrode array. In this time sequence, the packet of the secondsignal charge readout at time 180 is moved to the electrode HP2.Substantially simultaneously with this charge movement, the first signalcharge retained in the second field is moved to the electrode HS4. Thefirst signal charge thus retained by the electrode HS4 is then moved tothe electrode HS3.

By this re-arraying, the two rows of signal charges RGBGRGBG . . . ,read out from the lowermost end in FIG. 14 are put into order as thefirst field. The two rows of signal charges BGRGBGRG . . . , read outfrom above the two bottom rows are put into order as the second field.

This re-arraying is a technique used for the G-square RB completecheckered pattern in a honeycomb array. Any other arraying pattern maygive rise to unneeded re-arraying or differential timing. Thisre-arraying may be used for routine square pixels.

After the re-arraying, the drive signals φHS1, φHS3 and φHS2, φHS4 shownin FIG. 17, parts (A) and (B) are supplied to transfer the signalcharges retained on the horizontal transfer path 50 to the horizontaltransfer paths 56 and 58. The drive signals φHP1, φHP2 shown in parts(C) and (D) are supplied to the horizontal transfer paths 56 and 58. Thestart position is the position at which the potential is initiallychanged from the horizontal blanking period. The start positions of thedrive signals φHP1, φH2 are compared to those of the drive signals φHS1,φHS3, φHS2 and φHS4 and the drive signals φHP1, φHP2 are started withinthe period intervals of the drive signals φHS1, φHS3, φHS2 and φHS4 witha delay of one-half periods. Directly before outputting, the resetsignal φRS shown in part (E) is applied, whereby output time domains 182to 188 are obtained.

The horizontal transfer path 50 transfers, as signal charges, a dummyD1, a dummy D2, an optically black pixel OB1, an optically black pixelOB2, R, G, B, G, . . . , in this order.

The solid imaging device 44 converts the signal charges into analogvoltage signals to output the dummy D3, optically black pixel OB2, G, G,. . . , in the output time domains 182 to 188, as output signals OS1 ofFIG. 17, part (F). The device 44 also outputs the dummy D1, opticallyblack pixel OB1, R, B, in the output time domains 182 to 188, as outputsignals OS2 of part (G). By supplying the timings in this manner, theoutput signal OS1 on the horizontal transfer path 56 outputs the colorG, while the output signal OS2 on the horizontal transfer path 58outputs the color R/B.

If desired to switch the outputs, the drive signals φHS1 and φHS3 shownin FIG. 17, part (H), and the drive signals φHS2 and φHS4 shown in part(I) may be supplied with a delay of start positions corresponding to oneperiod interval 190 of these drive signals. The device 44 outputs thedummy D1, optically black pixel OB1, R, B, in the output time domains182 to 188, as output signal OS1 of part (J). The device 44 also outputsthe dummy D2, optically black pixel OB2, G, G, . . . , in the outputtime domains 182 to 188, as output signal OS2 of part (K).

In the present embodiment, the technique of delaying the drive signalφHS is used. This technique is not to be interpreted as restrictive andthe supply of the drive signal φHS may be started at a time earlier byone period interval.

By this operation, an output signal may readily be changed over withoutregard to prevailing driving modes.

With the device 44, the output amplifiers 60 and 62 are afforded withdifferential sensitivities in charge detection. Thus, during normalimaging, signal charges of the color G are supplied to and output fromthe output amplifier 60 of low detection sensitivity, while signalcharges of the colors R/B are supplied to and output from the outputamplifier 62 of high detection sensitivity. The device 44 thus preventssaturation of signal charges of the color G having the highestsensitivity, while amplifying output signals of the colors R/G withrespect to the output signal for the color G. In this manner, it ispossible with the device 44 to suppress the white balance gain to asmaller value to improve the S/N (signal to noise) ratio of the outputsignal.

In addition, the output signal of the color G is exploited incalculating for AE/AF control. In this case, the output signal for thecolor G may be switched so as to be output from the output amplifier 62of high detection sensitivity. In this case, the device 44 is able toamplify the signal quantity of the color G and to output the soamplified signal for the color G. This may improve the accuracy incalculating AE/AF control.

The operational timing for low speed driving in the device 44 will nowbe described. With the low speed driving, the drive signals φHS1, φHS2,φHS3 and φHS4 shown in FIG. 18, parts (A) and (B) are of the samefrequency as that of the drive signals φHP1 and φHP2 shown in parts (C)and (D). In case the drive signal φHS2 arriving at the last electrodeHS2 of the horizontal transfer path 50 is at level “L”, the drive signalφHP supplied to the electrode HP1 is at a level “H”, while the drivesignal φHP2 supplied to the electrode HP2 is at a level “L”. Hence, thesignal charges are transferred at all times via branching section (HSL)54 towards the electrode HP1, that is, towards the horizontal transferpath 56.

After application of the reset signal φRS shown in FIG. 18, part (E),the output signal OS1 shown in part (F) is output. The output signal OS2shown in part (G) is at “L” level, as a result of which the outputsignal OS1 is a single line output. Since the output signal OS2 is notused, the power supply for the output amplifier 62 may be turned off. Inthis case, supply of power for the amplifier power supply 16 iscontrolled depending on the control signal 86 from the power supplycontrol 122. The power supply 66 is turned off.

The phases of the drive signal φHP1 and φHP2 may be reversed from thoseshown, or the phase of the set of the drive signals φHS1 and φHS3 andthat of the set of the drive signals φHS2 and φHS4 may be reversed fromthose shown, so that, with the device 44, only the output amplifier 62will be in operation. By so doing, only the horizontal transfer path 58will be in operation (one-line outputting). It is possible in thisfashion to switch between one-line outputting and two-line outputting toenable free selection of the outputs. With low sensitivity, if thedynamic range is prioritized, it may be preferred to select the outputamplifier with low sensitivity. On the other hand, if the highsensitivity is prioritized, it may be preferred to select the outputamplifier with high sensitivity.

Referring to FIG. 19, the device 44 includes trifurcated horizontaltransfer paths 192, 194 and 196 for three line readout after a branchingsection (HSL) 54 provided from a horizontal transfer path 50. Outputamplifiers 198, 200 and 202 are provided at output sides of thehorizontal transfer paths 192, 194 and 196, respectively. The outputamplifiers 198, 200 and 202 may exhibit differential sensitivities incharge detection. On the horizontal transfer path 192, electrodes HP3,HP2, HP1 and HP2 are provided adjacent to the branching section 54. Onthe horizontal transfer path 194, electrodes HP2, HP4, HP2, HP4 and HP2are provided adjacent to the branching section 54. The number of theelectrodes on the horizontal transfer path 194 is larger by one thanthat on the horizontal transfer path 192. On the horizontal transferpath 196, electrodes HP1, HP2, HP3, HP2, HP1 and HP2 are providedadjacent to the branching section 54. The number of the electrodes onthe horizontal transfer path 196 is larger by one than that on thehorizontal transfer path 194.

The driving timing in the horizontal transfer for three line output willnow be described. On the horizontal transfer path 50, drive signals φHS1to φHS4 are supplied in the same way as above, as shown in FIG. 20,parts (A) and (B). On the horizontal transfer paths 192, 194 and 196,there is supplied a drive signals φHP1 to φHP4. The drive signal φHP2 ofpart (D) is the same as the drive signal φHP2 of FIG. 5, part (D). Thedrive signal φHP4 of FIG. 20, part (F), of the present embodiment is thesame as the drive signal φHP1 of FIG. 5, part (C). The frequency of thedrive signals φHP1 and φHP3 of FIG. 20, parts (C) and (E) is one-halfthat of the drive signals φHP2 and pHP4. The rising edge of the drivesignal φHP1 of FIG. 20, part (C), is synchronized with the rising edgeof the drive signal φHP4. As for the timing relationship of FIG. 20(E),the rising edge of the drive signal φHP3 is synchronized with thefalling edge of the drive signal φHP2.

On the horizontal transfer paths 192, 194 and 196, output signals aregenerated in the output time domains 204, 206, 208 responsive to thereset signal φRS of FIG. 20, part (G), supplied. The output signals OS1and OS3 shown in part (H) are output at every second output timedomains, that is, at output time domains 204, 208. The output signal OS1is an output signal of the color R, while the output signal OS3 is anoutput signal for the color B. The output signal OS2 shown in part (I)is output in every output time domain, that is, at the output timedomains 204, 206, 208. The output signal OS2 is an output signal for thecolor G.

By outputting from color to color in this fashion, it is possible toimprove the degree of freedom in color designing.

A device 44 shown in FIG. 21 includes horizontal transfer paths 210,212, 214 and 216 for four line readout connected to the horizontaltransfer path 50 via branching section (HSL) 54. The horizontal transferpaths 210, 212, 214 and 216 are provided at output ends with outputamplifiers 218, 220, 222 and 224, respectively. The output amplifiers218 and 222 are afforded with differential sensitivities in chargedetection. However, the output amplifiers 222 and 224 reading out thesame colors G_(r) and G_(b) are desirably adjusted to the samesensitivity for charge detection. The colors G_(r) and G_(b) mean thatthe color attributes of the color filter segments of the photosensitivecells 46 neighboring to the color G are the colors R and B.

In the horizontal transfer path 210, electrodes HP4, HP1, HP2, HP3 andHP4 are provided next to the branching section 54. In the horizontaltransfer path 212, electrodes HP3, HP4, HP1, HP2, HP3 and HP4 areprovided next to the branching section 54. The number of the electrodesof the horizontal transfer path 212 is one more than that of thehorizontal transfer path 210. In the horizontal transfer path 214,electrodes HP2, HP3, HP4, HP1, HP2, HP3 and HP4 are provided next to thebranching section 54. The number of the electrodes of the horizontaltransfer path 214 is one more than that of the horizontal transfer path212. In the horizontal transfer path 216, electrodes HP1, HP2, HP3, HP4,HP1, HP2, HP3 and HP4 are provided next to the branching section 54. Thenumber of the electrodes of the horizontal transfer path 216 is one morethan that of the horizontal transfer path 214.

The driving timing in the horizontal transfer of the four-line outputwill now be described. To the horizontal transfer path 50 are supplieddrive signals φHS1 to φHS4 which are the same as those described above,as shown in FIG. 22, parts (A) and (B). To the horizontal transfer paths210, 212, 214 and 216 following the branching, drive signals φHP1 topHP4 shown in parts (C) to (F) are supplied. The frequency of the drivesignals φHP1 to φHP4 is one-fourth that of the drive signals φHS1 toφHS4. The drive signals φHP2 to φHP4 are phase-shifted 90°, 180° and270° with respect to the rising edge of the drive signal φHP1. On thehorizontal transfer paths 210 to 216, output signals OS1 to 0S4 areobtained in the output time region 226 at the same time in keeping withthe reset signal φRS of part (G).

It is noted that, even in the device 44 for horizontal transfer forthree and four line readouts, it is possible to select two lines and tochange the driving pattern responsive to signal charges of the colorattributes to change over the output destinations. This suppresses theWB gain to improve the S/N ratio.

By this multi-line readout, it is possible to read out signal chargeswith a further lower driving frequency to improve the degree of freedomin color designing.

An alternative embodiment of the present invention will now be describedwith reference to the drawings. Referring now to FIG. 23 showing a solidstate imaging apparatus 10 a of the present modification, the timingsignal generator 32 controls the transfer timing on the horizontaltransfer path of the imaging unit 14, according to the measurement by atransfer efficiency measurement unit 500 of the signal processor 26. Inthe description, like components are designated with the same referencenumerals and description thereon will not be repeated for simplicity.

In the present solid state imaging apparatus 10 a, the speed ofhorizontal transfer of signal charges in the imaging unit 14 may bevaried depending on an image shooting mode, such as a still image mode,a moving picture mode or a repeated shooting mode, or on the result ofscene decision on an image being imaged. More specifically, with theinstant alternative embodiment, signal charge transfer may be made at ahigh or a low speed. In the low-speed transfer, the imaging unit 14outputs a sole shot image via a sole output circuit by way of one-lineoutputting. In the high-speed transfer, the imaging unit 14 outputs asole shot image via two output circuits by way of two-line outputting.

The device 44 transmits the drive signal φHS2, supplied from the drivers20, to respective electrodes of the transfer device HS2 on thehorizontal transfer path 50 to transmit the drive signal φHSL suppliedfrom the biasing circuit 18 to each electrode HSL of the branchingsection 54. The drive signal φHSL is a constant bias voltage. The device44 routes the drive signals φHP1 and φHP2 to transfer elements HP1 andHP2 on the horizontal transfer elements 56 and 58, respectively. Thedevice 44 also transmits drive signals φOG, φRS and φRD supplied fromthe drivers 20, to the electrodes OG and RS and to the reset drain RD,respectively. The electrode OG is supplied with a preset voltage by thisdrive signal φOG, while the reset drain RD is supplied with a presetpower supply voltage by the drive signal φRD.

The signal processor 26 has the function of generating a control signalresponsive to a digital signal 118. In the present alternativeembodiment, the signal processor 26 includes, in addition to thetransfer efficiency measurement unit 500, the power supply control 122,gain control 124, power supply control 122, AF control 126, AE control128, AWB control 130 and data converter 132 like the embodiment shown inand described with reference to FIG. 2.

The transfer efficiency measurement unit 500 measures the transferefficiency for signal charge proceeding from the branching section 54through the horizontal transfer paths 56 and 58, that is, the transferefficiency on the horizontal transfer paths 56 and 58, based on thedigital image signal 118.

The transfer efficiency measurement unit 500 measures the horizontaltransfer efficiency of the horizontal transfer paths 56 and 58 inadvance, for example, at the time of shipment from the plant.Preferably, it is verified whether the horizontal transfer efficiency ofone of the horizontal transfer paths is satisfactory, responsive to theresults of the measurement, and the result of decision is stored in amemory circuit, not shown. The transfer efficiency measurement unit 500may store the results of measurement, that is, the horizontal transferefficiency itself in the memory, for having the system controller 28check and verify the horizontal transfer efficiency.

The system controller 28 may also have the function of verifying, incase the transfer efficiency measurement unit 500 has stored themeasured results in a memory, which of the horizontal transfer paths hasthe optimum transfer efficiency, based on the result. The systemcontroller 28 sends a control signal representing the results ofdecision by the system controller 28 or by the transfer efficiencymeasurement unit 500 to the timing signal generator 32.

In the present alternative embodiment, the timing signal generator 32may receive the result of decision indicating which of the horizontaltransfer paths 56 and 58 has the optimum horizontal transfer efficiency,from the transfer efficiency measurement unit 500 or the systemcontroller 28, and vary the driving conditions for the horizontal timingsignal for the horizontal transfer path 50, based on the results ofdecision. For example, the timing signal generator 32 may shift thedriving start time in the initial driving condition for the horizontaltiming signal to make a relative shift from the driving start time inthe initial driving condition of the horizontal timing signal for thehorizontal transfer paths 56 and 58.

When a horizontal timing signal of the initial driving condition forhigh speed driving is supplied by the timing signal generator 32 to thedrivers 20 to control the horizontal transfer path 50 and the branchingsection 54, green signal charges are transferred to the horizontaltransfer path 56, while alternately red and blue signal charges aretransferred to the horizontal transfer path 58. If the horizontal timingsignal of the initial driving condition is supplied to the drivers 20,as the horizontal timing signal is relatively offset so as to be delayedor advanced by, for example, one period, such as to control thehorizontal transfer path 50 and the branching section 54, the signalcharges of the red and blue colors may be alternately transferred to thehorizontal transfer path 56, while the green signal charges may betransferred to the horizontal transfer path 58.

With the timing signal generator 32 of the present alternativeembodiment, it is possible to determine the driving condition forreversed branching, as the horizontal timing signal of the initialdriving condition is offset as described above, in order to reversesignal charges transferred on the horizontal transfer paths 56 and 58 byinvert electrical signals output to the output amplifiers 60 and 62.

The timing signal generator 32 may determine desired driving conditionsfor high speed driving, responsive to the results of decision of thehorizontal transfer efficiency, to transfer desired signal charges, suchas red and green signal charges, to one of the horizontal transfer paths56 and 58 where the horizontal transfer efficiency is optimum.

Moreover, during low speed driving, the timing signal generator 32transfers all signal charges only to one of the horizontal transferpaths 56 and 58. It is therefore possible to determine desired drivingconditions for low speed driving, responsive to the result of decisionof the horizontal transfer efficiency, and to transfer all signalcharges to the horizontal transfer efficiency 56 or 58 having theoptimum horizontal transfer efficiency. The horizontal transfer in theinitial driving conditions is carried out as described above withreference to FIGS. 4 to 9E.

The operation of horizontal transfer under an initial driving conditionduring high speed transfer in the solid state imaging apparatus 10 awill now be described with reference to the timing chart of FIG. 24.

FIG. 24, parts (A) to (G) illustrate the operation in which the timingsignal generator 32 transmits the horizontal timing signal of theinitial driving condition to the drivers 20. In the figure, parts (A)and (B) show drive signals φHS1 and φHS3, and drive signals φHS2 andφHS4, which the HS driver 96 outputs to the horizontal transfer path 50,respectively. Parts (C) and (D) show drive signals φHP1 and φHP2, the HSdriver 98 outputs to the horizontal transfer paths 56 and 58,respectively. Part (E) show the reset signal φRS, the RS driver 100outputs to the output amplifiers 60 and 62, while parts (F) and (G) showoutput signals OS1, OS2, output from the output amplifiers 60 and 62,respectively.

It is now assumed that, on the horizontal transfer path 50 of thepresent alternative embodiment, the signal charges transferred from eachvertical transfer path 48 are re-arrayed in the output sequence, duringthe horizontal blanking period. It is also assumed that, at a time t202,the dummy pixels D1, D2, optically black pixels OB1, OB2, R pixel, Gpixel, B pixel, G pixel, . . . are stored in this order, in therespective transfer elements transferred, beginning from the endneighboring to the branching section 54 to the opposite end.

In the alternative embodiment, the horizontal drive signals 74 actuatedat time t204 is generated by the HS driver 96 in the drivers 20 as shownin FIG. 3, responsive to the horizontal timing signal of the initialdriving condition. As this drive signal 74, the drive signals φHS1 andφHS3 and the drive signals φHS2 and φHS4 are transmitted to thehorizontal transfer path 50. There is also generated the horizontalparallel drive signal 76 actuated at time t206 in the HP driver 98 inthe drivers 20. As the drive signal 74, the drive signals φHP1 and φHP2are supplied to the horizontal transfer paths 56 and 58, respectively.

First, on the horizontal transfer path 50, the signal charges aretransferred horizontally towards the branching section 54. In thealternative embodiment, the signal charges are transferred in thesequence of the dummy pixels D1, D2, optically black pixels OB1, OB2, Rpixel, G pixel, B pixel, G pixel, . . . .

The signal charges are alternately transferred at this time from thebranching section 54 to the horizontal transfer paths 56 and 58, in abranched fashion. The branched transfer will be described subsequently.The signal charges are initially sent to the horizontal transfer path 58supplied with a horizontal parallel drive signal φHP2 which is at level“H” at time t204. The signal charges are then sent to the horizontaltransfer path 56 supplied with the horizontal parallel drive signal φHP1which is at level “H” at time t206. Thus, in the alternative embodiment,the dummy pixel D1, the optically black pixel OB1, R pixel and the Bpixel are transferred in this order towards the horizontal transfer path58, while the dummy pixel D2, the optically black pixel OB2, G pixel andthe G pixel are transferred in this order towards the horizontaltransfer path 56.

The signal charges sent to the horizontal transfer paths 56 and 58 aretransferred to the output amplifiers 60 and 62, respectively, where theyare converted into analog electrical signals which are then output. Theoutput amplifier 60 of the instant alternative embodiment sequentiallyoutputs the dummy pixel D2, the optically black pixel OB2, G pixel andthe G pixel, as output signal OS1, that is, as analog electrical signal82, during the output periods t182, t184, t186 and t188, respectively,as shown in FIG. 24, part (F).

On the other hand, the output amplifier 62 sequentially outputs thedummy pixel D2, dummy pixel D1, optically black pixel OB1, R pixel andthe B pixel, as output signal OS2, that is, as analog electrical signal84, during the output periods t182, t184, t186 and t188.

Thus, if the imaging unit 14 executes horizontal transfer under theinitial condition, the output signal OS1 indicating the color signal ofthe G pixel is output from the horizontal transfer path 56 and theoutput amplifier 60, while the output signal OS2 indicating the colorsignal of the R and B pixels is output from the horizontal transfer path58 and the output amplifier 62.

The operation of shifting the horizontal timing signal from the initialdriving condition for high-speed transfer in the solid state imagingapparatus 10 a of the present alternative embodiment will now bedescribed with reference to the timing chart shown in FIG. 25.

In FIG. 25, parts (A) to (G), there is shown the operation in which thetiming signal generator 32 sends to the drivers 20 a horizontal timingsignal of the driving condition of inverted branching, having a delay ofone period, e.g. a period t190 from the initial driving condition. Inthe figure, parts (A) and (B) show the drive signals φHS1 and φHS3, andthe drive signal φHS2 and φHS4 which the HS driver 96 outputs to thehorizontal transfer path 50, respectively. Parts (F) and (G) show outputsignals OS1 and OS2 output by the output amplifiers 60 and 62,respectively. It is noted that the drive signals φHP1 and φHP2 and thereset signal φRS may be the same signals as those shown in FIG. 24,parts (C), (D) and (E).

In the present alternative embodiment, it is again assumed that thedummy pixels D1 and D2, optically black pixels OB1 and OB2, R pixel, Gpixel, B pixel and the G pixel, . . . , are stored at time t202 in therespective transfer elements in the horizontal transfer path 50 in thesame manner as above.

In the instant alternative embodiment, the horizontal parallel drivesignal 76 actuated at time t206 is generated by the HP driver 98 in thesame manner as above. As this drive signal 76, the drive signals φHP1and φHP2 are supplied to the horizontal transfer paths 56 and 58,respectively. Moreover, the HS driver 96 generates the horizontalparallel drive signal 74 actuated at time t208 responsive to thehorizontal timing signal of the driving condition for invertedbranching. As this drive signal 74, the drive signals φHS1 and φHS3 andthe drive signals φHS2 and φHS4 are supplied to the horizontal transferpath 50.

Next, on the horizontal transfer path 50, the signal charges arehorizontally transferred towards the branching section 54. In thepresent alternative embodiment, the signal charges in the order of thedummy pixels D1, D2, optically black pixels OB1, OB2, R pixel, G pixel,B pixel, C pixel, . . . .

At this time, the signal charges are alternately transferred from thebranching section 54 to the horizontal transfer paths 56 and 58 in thesequence reversed from that of the horizontal transfer of the initialdriving condition. The signal charges are initially sent to thehorizontal transfer path 56 supplied with the horizontal parallel drivesignal φHP1 which is at level “H” at time t208, and are then sent to thehorizontal transfer path 58 supplied with the horizontal parallel drivesignal φHP2 which is at level “H” at time t210. Thus, in the presentalternative embodiment, the dummy pixel D1, optically black pixel OB1, Rpixel and the B pixel are sent in this sequence to the horizontaltransfer path 56, while the dummy pixel D2, optically black pixel OB2, Gpixel and the G pixel are sent in this sequence to the horizontaltransfer path 58.

The signal charges on the horizontal transfer paths 56 and 58 are thensent to the output amplifiers 60 and 62, respectively. The outputamplifier 60 outputs, as the output signal OS1, the dummy pixel D1,optically black pixel OB1, R pixel and the B pixel during the outputperiods t182, t184, t186 and t188, respectively, as shown in FIG. 25,part (F). On the other hand, the output amplifier 62 outputs, as theoutput signal OS2, the dummy pixel D2, optically black pixel OB2, Gpixel and the G pixel, during the output periods t182, t184, t186 andt188, respectively, as shown in part (G).

Thus, in case the imaging unit 14 executes horizontal transfer under thedriving condition of inverted branching, the horizontal transfer path 56and the output amplifier 60 output the output signal OS1 indicating thecolor signals of the R and B pixels, while the horizontal transfer path58 and the output amplifier 62 output the output signal OS2 indicatingthe color signals of the G pixels.

The operation of low-speed horizontal transfer by the solid stateimaging apparatus 10 a of the present alternative embodiment will now bedescribed with reference to the timing chart of FIG. 26.

FIG. 26, parts (A) to (G), show the operation in case the timing signalgenerator 32 sends a horizontal timing signal of the initial drivingcondition to the drivers 20. Specifically, in the figure, parts (A) and(B) show horizontal serial drive signals φHS1, φHS3 and φHS2, φHS4 whichthe HS driver 96 outputs to the horizontal transfer path 50. Parts (C)and (D) show the horizontal parallel drive signals φHP1 and φHP2, outputby the HP driver 98 to the horizontal transfer paths 56, 58,respectively. Part (E) shows the reset signal φRS the RS deriver 100outputs to the output amplifiers 60 and 62, and parts (F) and (G) showoutput signals OS1 and OS2 output from the output amplifiers 60 and 62,respectively.

In the present alternative embodiment, the horizontal serial drivesignals φHS1, φHS3 and φHS2, φHS4 are output at the same frequency asthat of the horizontal parallel drive signals φHP1 and φHP2. Referringto FIG. 26, when the drive signal φHS2 supplied to the last electrodeHS2 of the horizontal transfer path 50 becomes “L” in level at timet212, while the drive signal φHP1 supplied to the electrode HP1 becomes“L” in level. The signal charges at the trailing end electrode HS2 aretransferred at all times via branching section (HSL) 54 to the electrodeHP1, that is, towards the horizontal transfer path 56.

With the device 44, the output amplifier 60 supplies an output signalOS1 indicating the color signal as shown in FIG. 26, part (F), while theoutput amplifier 60 supplies an output signal OS2 indicating the level“L” as shown in part (G).

Thus, during low speed driving, the device 44 supplies only the outputsignal OS1 on a single line without using the output signal OS2. Hence,the power supply of the output amplifier 62 may be turned off. It ispreferred in this case to control the supply of the supply power of theamplifier power supply 16, responsive to the control signal 86 from thepower supply control 122, to turn off the power supply 66.

During low-speed horizontal transfer, the system controller 28 and thetiming signal generator 32 may control the drivers 20 to reverse thephase of the drive signals φHP1 and φHP2 or to reverse the phase of thedrive signals φHS1, φHS3 and the phase of the drive signals φHS2, φHS4.By so doing, the device 44 may actuate only the horizontal transfer path58 and the output amplifier 62 to output the output signal OS2 by soleline output.

By so doing, it is possible to switch between the one-line outputtingand the two-line outputting extremely readily to make free outputselection. If dynamic range preference is selected in case of lowsensitivity, it is preferred to select the output amplifier with lowsensitivity in charge detection, whereas, if sensitivity preference isselected in case of high sensitivity, it is preferred to select theoutput amplifier with high sensitivity in charge detection.

A further alternative embodiment of the operation of measuring thetransfer efficiency in the solid state imaging apparatus 10 a will nowbe described.

In the present apparatus 10 a, signal charges are mixed on thehorizontal transfer path 50 by horizontal pixel mixing, for measuringthe transfer efficiency on the branching section 54 and on thehorizontal transfer paths 56 and 58. The drivers 20 control the drivingof the imaging unit 14 in order to provide for two-channel outputting onthe branching section 54 and on the horizontal transfer paths 56 and 58.

By this horizontal pixel mixing, the horizontal transfer path 50accumulates a pixel of a reference signal, obtained on mixing pluralsignal charges, and void pixels, deprived of signal charges by thismixing. The horizontal transfer path 50 repeatedly generates pixelgroups 250, each composed of plural pixels, more specifically, eachcomposed of the pixel of the reference signal Sig followed by two ormore void pixels Emp1 and Emp2. The horizontal transfer path 50horizontally transfers the pixel groups 250, each made up of the pixelSig, Emp1 and Emp2, towards the branching section 54.

In case the branching section 54 and the horizontal transfer paths 56and 58 are driving-controlled, responsive, e.g. to the horizontal timingsignal of the initial driving condition, the branching section 54 sendsthe pixel Sig and the second void pixel Emp2 to the horizontal transferpath 56, while sending the first void pixel Emp1 to the horizontaltransfer path 58.

In this case, the signal charge left over at the time of transfer of thepixel Sig of the reference signal in the course of horizontal transferon the horizontal transfer path 56 is intruded into the second voidpixel Emp2, while the signal charge left over at the time of transfer ofthe pixel Sig of the reference signal in the course of horizontaltransfer from the branching section 54 onto the horizontal transfer path58 is intruded into the first void pixel Emp1.

The amount of signal charges combined from the first void pixel Emp1 andthe second void pixel Emp2, that is, the amount of the residual charges232, left over on the horizontal transfer path 56 until the pixel Siggets to the output amplifier 60, as it travels from the branchingsection 54 through the horizontal transfer path 56, is varied with thepixel Sig of the reference signal, that is, with the quantity of thereference signal charges.

The output amplifier 60 then outputs the output signal 82 including thepixel Sig of the reference signal and the second void pixel Emp2. Thepre-processor 22 generates a digital signal 110 by processing thisoutput 82 to store the digital signal in the memory 24. In similarmanner, the horizontal transfer path 58 and the output amplifier 62output the output signal 84 including the first void pixel Emp1, and thepre-processor 22 generates a digital signal 112 by processing thisoutput 84 to store the digital signal 112 in the memory 24.

The signal processor 26 reads out the pixel of the reference signal Sigand the first and second void pixels Emp1 and Emp2 from the memory 24,as digital signal 118, over bus 114 and signal line 120.

In the signal processor 26, the transfer efficiency measurement unit 500may acquire a residual transfer charge quantity 232 on the horizontaltransfer path 56, based on the first void pixel Emp1 and the secondvacant pixel Emp2. The transfer efficiency measurement unit may thencalculate the horizontal transfer efficiency HTR11 pertinent to transferfrom the branching section 54 to the horizontal transfer path 56, of thehorizontal transfer efficiency (HTR) on the horizontal transfer path 56,based on the charge of the reference signal Sig and the residualtransfer charge Emp1. The transfer efficiency measurement unit also maycalculate the horizontal transfer efficiency HTR12 pertinent to thetransfer on the horizontal transfer path 56 up to the electrode OG andthe section FD, based on the quantity of the charge of the referencesignal Sig and that of the residual transfer charge Emp2. The transferefficiency measurement unit 500 may calculate the horizontal transferefficiency HTR11, using an expression:

HTR11=(Sig−Emp1)/Sig×100, while it may calculate the horizontal transferefficiency HTR12, using an expression:HTR12=(Sig−Emp2)/Sig×100. The horizontal transfer efficiencies HTR11 andHTR12 are varied responsive to the charge quantity of the referencesignal Sig as shown in FIG. 30.

In case the branching section 54 and the horizontal transfer paths 56and 58 are driving-controlled under the driving condition of reversedbranching, with the horizontal timing signal being offset from that ofthe initial driving condition, the branching section 54 sends the firstvoid pixel Emp1 to the horizontal transfer path 58, while sending thepixel of the reference signal Sig and the second void pixel Emp2 to thehorizontal transfer path 56.

The signal charge left over at the time of transfer of the pixel Sig ofthe reference signal, in the course of horizontal transfer on thehorizontal transfer path 58 from the branching section 54 is intrudedinto the first void pixel Emp1, while the signal charge left over at thetime of transfer of the pixel Sig of the reference signal in the courseof horizontal transfer from the branching section 54 onto the horizontaltransfer path 58 is intruded into the second void pixel Emp2. The amountof signal charges combined from the void pixels Emp1 and Emp2, that is,the amount of the residual charge 232 left over on the horizontaltransfer path 58 until the pixel Sig gets to the output amplifier 62, asit travels from the branching section 54 through the horizontal transferpath 58 is varied with the quantity of the reference signal charges asshown in FIG. 29.

The output amplifiers 60, 62 then output the output signal 82 includingthe first void pixel Emp1, and the output signal 84 including the pixelof the reference signal Sig and the second void pixel Emp2. Thepre-processor 22 stores digital signals 110, 112, derived from theoutput signals 82 and 84, respectively, in the memory 24.

The signal processor 26 reads out the first void pixel Emp1, pixel ofthe reference signal Sig and the second void pixel Emp2 from the memory24 as digital signal 118, over a bus 114 and a signal line 120.

In the signal processor 26, the transfer efficiency measurement unit 500may acquire a residual transfer charge quantity 234 on the horizontaltransfer path 58, based on the first vacant pixel Emp1 and the secondvacant pixel Emp2. The transfer efficiency measurement unit may thencalculate the horizontal transfer efficiency HTR21 pertinent to transferfrom the branching section 54 to the horizontal transfer path 58, out ofthe horizontal transfer efficiency (HTR) on the horizontal transfer path58, based on the charge of the reference signal Sig and the residualtransfer charge Emp1. The transfer efficiency measurement unit also maycalculate the horizontal transfer efficiency HTR12 pertinent to transferon the horizontal transfer path 58 up to the electrode OG and thesection FD, based on the charge of the reference signal Sig and theresidual transfer charge Emp2. The transfer efficiency measurement unit500 may calculate the horizontal transfer efficiency HTR21, using anexpression: HTR21=(Sig−Emp1)/Sig×100, while it may calculate thehorizontal transfer efficiency HTR22, using an expression:

HTR22=(Sig−Emp2)/Sig×100. The horizontal transfer efficiency HTR21 andthe horizontal transfer efficiency HTR22 are varied responsive to thecharge of the reference signal Sig as plotted in FIG. 30.

The transfer efficiency measurement unit 500 may measure one or both ofthe horizontal transfer efficiencies HTR11 and HTR12, while it may alsocalculate one or both of the horizontal transfer efficiencies HTR21 andHTR22, and use the measured results for determining the horizontaltransfer efficiencies of the horizontal transfer paths 56 and 58. In thepresent alternative embodiment, it is particularly preferred to decideon the horizontal transfer efficiency based on the amount of residualcharges left over from R and B pixels to the G pixel at the branchingsection 54, and to measure only the residual transfer chargeattributable to the branching section 54, that is, the horizontaltransfer efficiencies HTR11 and HTR22, for use in determining thehorizontal transfer efficiency.

The transfer efficiency measurement unit 500 may compare the horizontaltransfer efficiencies HTR11 and HTR21 to verify which of the horizontaltransfer paths 56 and 58 is better in the transfer efficiency. It isnoted that the transfer efficiency measurement unit 500 may compare thehorizontal transfer efficiencies HTR11 and HTR21 based on the quantityof the charges at a sole point, or may calculate evaluation values ofthe horizontal transfer efficiencies HTR11 and HTR21 based on thequantities of the charges at plural points.

The present apparatus 10 a captures a preset subject in advance tomeasure the transfer efficiency. In the present alternative embodiment,the apparatus may capture plural different subjects to obtain referencesignal charge quantities and residual charges at plural points. Thetransfer efficiency measurement unit 500 may then calculate thehorizontal transfer efficiencies HTR11 and HTR21 at plural points forcomparison and verification.

In the present alternative embodiment, a plural number of groups 250,each made up of a pixel of a reference signal Sig followed by two ormore void pixels Emp1 and Emp2, may be generated in succession byhorizontal pixel mixing on the horizontal transfer path 50. To this end,the horizontal transfer path 50 may be driven in a horizontal eightpixel mixing system to formulate the pixel group 250 each made up of apixel of a reference signal Sig followed by three void pixels Emp1, Emp2and Emp3.

The operation of driving the horizontal transfer path 50 in accordancewith the horizontal eight pixel mixing system, in the solid stateimaging apparatus 10 a of the present alternative embodiment, will nowbe described with reference to the timing chart of FIG. 30 and potentialtransition diagrams of FIGS. 32A through 32I.

In the potential transition diagrams of FIG. 32A through 32I, there areshown the potential levels and signal charges retained on the horizontaltransfer path 50. Transfer elements HS4, HS1, HS2, HS3, HS2, HS1, HS4,HS3 and HS4 are formed in the transfer path 50 in this sequence from itsend neighboring to the branching section 54 towards its opposite end.The signal charge of each transfer element is transferred towards left,that is, towards the forward side transfer element.

On the horizontal transfer path 50 of the present alternativeembodiment, horizontal eight pixel mixing is carried out during thehorizontal blanking period such that signal charges of the group 250composed of the transfer elements H51, HS2, HS3, HS2, HS1, HS4, HS3 andHS4 are mixed together. Referring to FIG. 31, part (A), signal chargesare transferred to the horizontal transfer path 50, responsive to thedrive signal φLM supplied to the line memory LM. The signal charges aremixed together on the horizontal transfer path 50, under driving controlby the horizontal serial drive signals 74, such as drive signals φHS1,φHS2 and φHS3, φHS4, supplied from the HS driver 96, as shown in FIG.31, parts (B) to (E).

When the drive signal φLM shown in FIG. 31, part (A), becomes “H” inlevel at time t302, signal charges are transferred from the line memoryLM to the packets generated directly underneath the electrodes of thetransfer elements HS1 to HS4 on the horizontal transfer path 50, becausethe drive signals φLM and the signals φHS1 to φHS4 shown in FIG. 31,parts (B) to (E) are all at level “H”. Referring to FIG. 32A, thepotential level of each of the transfer elements HS1 to HS4 in the stateof time t302 is reference level 300.

If the level “L” drive signals φHS2, φHS4 are then supplied at time t304to the transfer elements HS2 and HS4, the potential level becomes higherat the transfer elements HS2 and HS4 as shown in FIG. 32B, so that thesignal charges are transferred to the forward side transfer elements HS1and HS3.

At time t306, the drive signal φHS4 at level “H” is supplied to thetransfer element HS4, so that the potential level reverts to thereference level 300.

If the level “L” drive signal φHS3 is then supplied at time t308 to thetransfer element HS3 as shown in FIG. 32D, the potential level becomeshigher at the transfer element HS3. Thus, if the forward side transferelement is HS2, which is of the same potential level, the signal chargeis maintained at the transfer element HS3. However, if the forward sidetransfer element is HS4, which is low in potential level, the signalcharge at the transfer element HS3 is transferred.

At time t310, the drive signal φHS4 at level “L” is supplied to thetransfer element HS4 to raise the potential level as shown in FIG. 32E,so that the retained signal charges are transferred to the forward sidetransfer element HS1.

At time t312, the level “L” drive signal φHS1 is supplied to thetransfer element HS1 to raise the potential level as shown in FIG. 32F.The level “H” drive signal φHS2 is supplied to the transfer element HS2so that the potential level reverts to the reference level 300. Thesignal charge is transferred from the high potential level transferelement HS1 to the forward side low potential level transfer elementHS2. A signal charge is also transferred from the rearward highpotential level transfer element HS3 to the transfer element HS2 whichhas become lower in potential level.

At time t314, the level “L” drive signal φHS2 is supplied to thetransfer element HS2 to raise the potential level as shown in FIG. 32G.The level “H” drive signal φHS3 is supplied to the transfer element HS3so that the potential level reverts to the reference level 300. Thesignal charge is transferred from the high potential level transferelement HS2 to the forward side low potential level transfer elementHS3.

At time t316, the level “H” drive signal φHS2 is supplied to thetransfer element HS2, so that the potential level reverts to thereference level 300 as shown in FIG. 32H. The level “L” drive signalφHS3 is supplied to the transfer element HS3 to raise the potentiallevel. The signal charge is transferred from the high potential leveltransfer element HS3 to the forward side low potential level transferelement HS2.

At time t318, the level “H” drive signal φHS1 is supplied to thetransfer element HS1, so that the potential level reverts to thereference level 300 as shown in FIG. 32I. The level “L” drive signalφHS2 is supplied to the transfer element HS2 to raise the potentiallevel. The signal charge is transferred from the high potential leveltransfer element HS2 to the forward side low potential level transferelement HS1.

In this manner, the signal charges of the group 250 composed of thetransfer elements HS1, HS2, HS3, HS2, HS1, HS4, HS3 and HS4, aretransferred to the foremost transfer element HS1, as the signal chargesundergo the horizontal eight pixel mixing process.

The pre-processor 22 may be composed of a G pixel processor 352 suitedfor processing G pixels, and an RB pixel processor 354 suited forprocessing R and B pixels as shown in FIG. 35. It is necessary in thiscase to supply an electrical signal of the G pixel and an electricalsignal of the R and B pixels, out of the electrical signals 82 and 84supplied from the imaging unit 14, to the G pixel processor 352 and tothe RB pixel processor 354, respectively.

In the present alternative embodiment, output units 362, 364 areconnected to the output amplifiers 60 and 62 of the imaging unit 14. Aconnection unit 372 and another connection unit 374 are connected to theconnection line 82 outputting the aforementioned electrical signal, anda connection unit 376 is connected to the connection line 84 outputtingthe aforementioned electrical signal. The electrical connection betweenthe connection units and the output amplifiers is changed responsive tomeasured results by the transfer efficiency measurement unit 500.

The transfer efficiency of the imaging unit 14 is measured by, e.g. atest on a silicon wafer (probe test). Based on the results ofmeasurement of the transfer efficiency, it is verified which of thehorizontal transfer paths 56 and 58 has a better transfer efficiency. Ifit is the horizontal transfer path 58 that has a better transferefficiency, the output unit 362 may be connected to the connection unit372, while the output unit 364 may be connected to the connection unit374 as shown in FIG. 35. If conversely the horizontal transfer path 56has the better transfer efficiency, the output unit 362 may be connectedto the connection unit 374, while the output unit 364 may be connectedto the connection unit 376 as shown in FIG. 36.

By so doing, when the present apparatus 10 a is operated with high-speeddriving, the output signal 82 of the imaging unit 14 is at all times forthe G pixel, which is processed by the G pixel processor 352, while theoutput signal 84 is at all times for the R pixel and the B pixel, whichare processed by the RB pixel processor 354. It is therefore possible toavoid switching of the processing or the electrical connection outsidethe imaging unit 14.

In the imaging unit 14, the output units 362 and 364 and the connectionunits 372, 374 and 376 may be formed by bonding pads, while connectionlines 382, 384 interconnecting the connection and output units may beformed by wires the connections of which may be changed as desired. Itis necessary for these wires 382, 384 to be connected without physicalcontact or intersection in order to avoid cross-talk in the transmittedsignals.

In case the present apparatus 10 a is used for capturing a subj ect withlow color temperature, for example, the signal charge obtained at the Rpixel photosensitive cell is great and that at the B pixelphotosensitive cell is small. If the signal charges are transferred inthe order of the R pixel, G1 pixel, B pixel and the G2 pixel on thehorizontal transfer path 50 towards the branching section 54, the amountof the charge left over by the forward side R pixel and intruded intothe rear side G1 pixel is greater than the amount of charge mixing thatoccurs between the forward side B pixel and the rear side G2 pixel. Thisis because the amount of charge mixing, that is, the amount of residualtransfer charges, is increased with increase in the signal quantity asshown in FIG. 29. Hence, there is produced the difference between thesignal quantity of the G1 pixel and that of the G2 pixel, even thoughthe pixels are of the same color, this difference in the signal quantityaffecting the ultimate image as a fixed pattern noise.

With the solid state imaging apparatus 10 a of the present invention, inwhich, when the signal charges are sent from the branching section 54via horizontal transfer paths 56 or 58 and output from the outputamplifier 60 or 62, the R and B pixels, in particular, are output on thehorizontal transfer path with higher transfer efficiency, it is possibleto prevent charges from being left over from the R and B pixels toprevent charge mixing into the G pixel.

A further modification of the present invention will now be described.In this modification, deterioration in the transfer efficiency in thebranching electrode is to be precluded. In the present alternativeembodiment, two horizontal transfer paths 56 and 58 are connected to thebranching section 54, which branching section divides signal chargesinto two parts which are to be supplied to the horizontal transfer paths56 and 58. The present invention is, however, not limited to thisconfiguration. That is, the number of the horizontal transfer pathsprovided in the branching section may be optionally set, and branchingmay optionally be made in keeping with the number of the horizontaltransfer paths.

In the solid state imaging device 44 including the branching section 54,analog electrical signals are read out, for example, in the followingmanner. FIG. 35 schematically shows the horizontal transfer paths of thedevice in a plane view. FIG. 36, part (A), schematically shows thehorizontal transfer paths 50 and 56 shown in FIG. 35, to an enlargedscale. FIG. 36, part (B), schematically shows, in cross-section, takenalong a chain-dotted line XXXVI-XXXVI in part (A). FIG. 37, part (A),schematically shows the horizontal transfer paths 50 and 58 shown inFIG. 35, to an enlarged scale. FIG. 37, part (B), schematically shows,in cross-section, the horizontal transfer paths 50 and 58, taken along achain-dotted line XXXVII-XXXVII in part (A).

In the present alternative embodiment, signal charges are transferred onthe horizontal transfer path 50 in the order of the G, R, G, B in termsof the color attributes. In the branching section 54, the signal chargeswith the color attributes of R and B are branched to the horizontaltransfer path 56, while the signal charges with the color attributes ofG are branched to the horizontal transfer path 58. A plural number ofthe transfer elements are formed on the horizontal transfer paths 50, 56and 58. Each transfer element is made up of two electrodes ofpolycrystalline silicon (polysilicon) and two impurity layers in thevicinity of the surface of the silicon substrate. The two impuritylayers lying underneath the two electrodes differ from each other inconstitution. Thus, when the equi-potential drive signals are applied,stepped potential levels are generated. The branching section 54 issimilarly a transfer element including two electrodes. In the following,the transfer element and the two electrodes included in the element aredenoted by the same reference numeral. For example, the branchingsection 54 denotes the transfer element, while the electrode 54 denotestwo electrodes of the branching section 54.

On the horizontal transfer path 50, there are formed polysiliconelectrodes HS2, HS1, HS4, HS3, HS4, HS1, HS2 and HS3 in this order fromthe right side towards the electrode HSL of the branching section 54lying on the left side as shown in FIG. 35. This set of the polysiliconelectrodes constitutes a repetitive unit. An electrode HL is providedadjacent to the right side of the electrode HSL, that is, adjacent tothe left side of the electrode HS3 on the output end of the horizontaltransfer path 50 in FIG. 35. The electrode HL is equivalent to theelectrode HS2 on the right side of the electrode HLS in FIGS. 4 and 6 to8. The electrode HL will be described in detail subsequently.

On the horizontal transfer path 56, there are sequentially formed fourpolysilicon electrodes HP1, HP2, HP1, HP2 and an OG (output gate)electrode, from the electrode HSL of the branching section 54 towardsthe output amplifier 60, as shown in FIGS. 37 and 38.

On the horizontal transfer path 58, there are sequentially arranged fivepolysilicon electrodes HP2, HP1, HP2, HP1, HP2 and an OG (output gate)electrode, from the electrode HSL of the branching section 54 towardsthe output amplifier 62, as shown in FIGS. 37 and 39.

Directly below the electrodes within the P-type silicon substrate notshown, there are formed impurity layers, as shown from imaginarycross-sectional surfaces of the left end reset drain RD to the electrodeHP1 of the horizontal transfer path 56 and thence further to theelectrode HL of the horizontal transfer path 56, as indicated from achain-dotted line XXXVI-XXXVI of FIG. 36.

Turning to the drive signal supplied to the respective electrodes, drivesignals φHS1, φHS2 and φHS3 and φHS4 are supplied to the electrodes HS1,HS2, HS3 and HS4, respectively. The drive signal φHSL is supplied to theelectrode HSL, in a manner not shown, and is a constant bias voltage.The drive signal φHL is supplied to the electrode HL. The timing forthese drive signals is shown in FIG. 38.

The flow of signal charges transferred horizontally by those drivesignals will now be described. FIGS. 41A through 41E and 42 show thepotential levels generated on the horizontal transfer paths 50, 56 and58 when the drive signals are applied thereto. FIG. 43 shows the stateof signal charge transfer at this time, as seen from above thehorizontal transfer paths. The timings shown in FIGS. 41A through 41E,42 and 43 correspond to those shown in FIG. 38. For example, the timingof FIG. 41A, FIG. 42, part (A) and 43A corresponds to time t=1 in FIG.38. The same applies for the other timings as well.

FIG. 39 shows the potential for the horizontal transfer paths 50 and 56.A simplified diagram of FIG. 36, part (B), is also shown in FIG. 39 forshowing the potential level positions. Similarly, FIG. 40 shows thepotential for the horizontal transfer paths 50 and 58. A simplifieddiagram of FIG. 37, part (B), is also shown in FIG. 40 for showing thepotential level positions. FIGS. 41A through 41E, 42 and 43 aresubstantially the same as FIGS. 4 and 6 through 9E and hence thedescription therefor is dispensed with.

Heretofore, the solid state imaging unit 44 suffers from the problemthat, if the transfer efficiency is deteriorated in the branchingsection 54, the signal charges left over affect signal charges of theremaining pixels, with the signal charges thus left over becoming afixed pattern noise in the image formed.

Specifically, assuming a case in which signal charges transferred in thesequence of color attributes G, R, G, B, are branched at the branchingsection 54, and the signal charges R and B are transferred on thehorizontal transfer path 50, while the signal charge G is transferred onthe horizontal transfer path 58, as shown in FIGS. 41A through 41E, 42and 43. When the deterioration in the transfer efficiency, that is,transfer deterioration, has occurred on the branching section 54, partof the signal charge R left over is mixed into the next signal charge,that is, the signal charge G. In particular, if the signal charges arethose obtained on shooting a subject having a low color temperature, thesignal charge R mixed in the signal charge G is increased, while thesignal charge B mixed in the signal charge G is decreased. Hence, adifference in the amounts of signal charges G transferred on thehorizontal transfer path 58 is produced and represented as a fixedpattern noise on the image.

Thus, in the present example, an electrode HL is provided directly infront of the branching section, and adapted for being drivenindependently. The duty cycle and/or the cycle of the drive signal φHLsupplied to the electrode HL is changed by the timing signal generator32 in order to provide for longer transfer time of the signal chargesfrom this electrode to the branching section. Moreover, in the presentexample, the duty cycle and/or the cycle of one or both of thehorizontal drive signals 76 a and 76 b driving the horizontal transferpaths 56 and 58, respectively is varied in the timing signal generator32 in order to provide for a longer signal charge transfer time from thebranching section to one of the horizontal transfer paths longer thanthe usual transfer time.

The usual transfer time is the transfer time prior to changing of theduty cycle and/or the cycle of the drive signal, and means the transfertime in case no transfer efficiency deterioration has occurred, that is,in case the transfer efficiency is maintained. In terms of the dutycycle, for example, the usual transfer time in the present example meansthe transfer time in case the duty cycle is 50%, that is, in case thehigh level time is about equal to the low level time. It is noted thatthe usual transfer time is not limited to that for the duty cycle of50%, insofar as the transfer efficiency is maintained.

In FIG. 36, the electrode HL is a transfer element, provided one infront of the electrode HSL of the branching section, and transfers thesignal charge received from the electrode HS3, to the electrode HSL. Inthe present example, the electrode HL is a pair of polysiliconelectrodes arranged as a set, as are the other electrodes. In addition,the electrode HL may be actuated independently. In the present example,a drive signal φHL is supplied to the electrode HL as shown in FIG. 7.

The drive signal φHL shown in FIG. 38 is the drive signal φHL suppliedto the electrode HL during the usual driving time. In the presentexample, the drive signal φHL during the usual driving is of the samesignal waveform as the drive signals φHS2, φHS4. The reason is that,since the electrode of the right side neighbor of the electrode HL isthe electrode HS3, it is necessary to provide for the same potential asthat of the electrodes HS2 and HS4 during usual driving. However, thepresent invention is not limited to this and the drive signal to besupplied to the electrode HL may be optionally set depending on thehorizontal transfer path 50. For example, the drive signal φHL duringthe usual driving may be the signal of the same waveform as the drivesignals φHS1 and φHS3.

If, in the present example, there is fear of transfer deterioration, asin the case of a low color temperature of the subject, the timing signalgenerator 32 changes the duty cycle of the drive signal φHL as shown inFIG. 42. By so doing, the signal charge transfer time from the electrodeHL to the electrode HSL may be made longer than the transfer time forthe usual transfer time, that is, the transfer time for the case of notchanging the duty cycle.

FIG. 42 depicts a timing chart schematically showing the timing of thedrive signals to be supplied to the respective electrodes shown in FIG.35. Specifically, FIG. 42 schematically shows the processing in whichthe duty cycle of the drive signal supplied to the electrode HL on theoccasion of deterioration in the transfer efficiency is changed so thatthe signal charge transfer time from the electrode HL to the electrodeHSL is made longer than that prior to duty cycle change, such as toprohibit deterioration in the transfer efficiency.

In FIG. 42, the drive signal φHL has a low level time longer than thehigh level time. Referring more specifically to FIG. 42, the high leveltime and the low level time of the drive signal φHL are both time Ta,that is, one-half period, in the previous example. In the presentexample, the low level time is the time Tb, while the high level time isthe time Tc. Since the time Ta is the one-half period, the relationship,time Tb>time Ta>time Tc, is established.

In the example shown in FIG. 42, the period is not modulated. The drivesignals φHS1 to φHS4 also are not modulated. It is because the transferefficiency on the horizontal transfer path 50 is to be maintained.However, the present invention is not limited to this and, for example,the drive signals φHS1 to φHS4 may be modulated. This drive signalmodulation becomes possible by the system controller 28 controlling thetiming signal generator 32, as an example.

The signal charges are transferred from the electrode HL to theelectrode HSL when the drive signal φHL is low in level and the drivesignal φHP1 is high in level. Thus, if the duty cycle of the drivesignal φHL is varied as described above to provide for the high leveltime Tb of the drive signal φHL longer than its low level time Tc, itbecomes possible to set the signal charge transfer time from theelectrode HL to the electrode HSL from time Ta to time Tb which islonger than time Ta. The result is that the signal charge transfer fromthe electrode HS to the electrode HSL may be better and the amount ofcharges left over untransferred may be decreased to eliminate theproblem of deterioration in the transfer efficiency.

By changing the duty cycle of the drive signal φHL in this manner, thehigh level time in the drive signal φHL may be shorter, so that thetransfer time to the electrode HL from the electrode as the left sideneighbor of the electrode HL may be shorter. For example, in the exampleof FIG. 35, the signal charge transfer time from the electrode HS3 tothe electrode HL becomes shorter. However, there is sufficient allowancein frequency characteristics in transferring signal charges from theelectrode HS3 to the electrode HS, so that there is sufficient margin indecreasing the transfer time. Hence, transfer may be achievedunobjectionably by applying this margin to the transfer time from theelectrode HS to the electrode HSL.

It is noted that the present invention is not limited to changing theduty cycle of the drive signal φHL. More specifically, the duty cycleand the period of each of the drive signal φHL, horizontal drive signalφHP1 and the horizontal drive signal φHP2 may be changed by the timingsignal generator 32, as shown for example in FIG. 43, in order toprovide for a longer signal charge transfer time from the branchingsection to one of the horizontal transfer paths.

FIG. 43 is a timing chart schematically showing another timing of thedrive signals supplied to the electrodes shown in FIG. 35 in case oftransfer efficiency deterioration. Specifically, FIG. 43 schematicallyshows the processing for eliminating the transfer efficiencydeterioration, according to which the duty cycle and the period of thedrive signal φHL, horizontal drive signals φHP1 and φHP2 are changed sothat the transfer time of signal charges from the electrode HSL to thehorizontal transfer path 56 in case of transfer efficiency deteriorationwill be longer than that before such change, such as to eliminate thetransfer efficiency deterioration. In FIG. 43, the same referencenumerals as those used in FIG. 42 denote the same or equivalentcomponent parts.

In the example shown in FIG. 43, not only the duty cycle of the drivesignal φHL but also that of each of the drive signals φHP1 and φHP2 ischanged. More specifically, the duty cycle of the drive signals φHP1 andφHP2 is changed in FIG. 43 so that, in the drive signal φHP1, the highlevel time is changed from time Td to time Tp and the low level time ischanged from time Te to time Tq. On the other hand, since the drivesignal φHP2 is reverse-phased from the drive signal φHP1, its low leveltime and high level time are set to time Tp and Tq, respectively.Meanwhile, since the pre-change time Td is about equal in length aspre-change time Te, and is equal to one-half the period of each of thedrive signals φHP1 and φHP2, the time Td, Te, Tp and Tg are related toone another by Tp>Td, Te>Tq.

In keeping with such changes in the drive signals φHP1 and φHP2, theperiod of the drive signal φHL is changed, so that the signal part withthe period equal to Tp and that with the period equal to Tq will appearalternately. In the example shown in FIG. 43, the duty cycle of thedrive signal φHL is set so that the low level period is loner than thehigh level period as in FIG. 42. For example, in the present example, ina signal part with one period equal to time Tp, the low level time istime Tl, while the high level time is time Tm, with Tl>Tm, whereas, in asignal part with one period equal to time Tq, the low level time is timeTn, while the high level time is time To, with Tn>To.

In the present example, even though the period of the drive signal φHLdiffers from one signal part to the next, the duty cycle of the signalpart with the period equal to time Tp is made equal to that of thesignal part with the period equal to time Tq. In more detail, if, in thesignal part where the period is equal to Tp, the low-level time Tl is60% of time Tp and the high-level time Tm is 40% of time Tp, thelow-level time Tn is 60% of time Tq and the high-level time To is 40% oftime Tq. However, the present invention is not limited to this and maybe modified optionally. For example, the duty cycle may be changed forthe signal part with the period equal to Tp and for the signal part withthe period equal to Tq. Alternatively, the duty cycle may be set to 50%for both of the signal parts and the lengths of both the low level timeand the high level time may be equal to one half period, only by way ofillustration.

The period of each of the drive signals φHS1 to φHS4 is also changedwith change in the drive signal φHL. Specifically, one period of each ofthe drive signals φHS1 to φHS4 in register with the signal part of thedrive signal φHL with the period of Tp is set to time T3 which is aboutequal to time Tp. In similar manner, one period of each of the drivesignals φHS1 to φHS4 in register with the signal part of the drivesignal φHL with the period of Tq is set to time T4 which is about equalto time Tq. It is noted that, in each cycle, the low and high levels areeach of one-half cycle, without the duty cycle being changed.

Suppose that the duty cycle of the drive signals φHP1 and φHP2 ischanged in this manner, so that the high level time of the drive signalφHP1 is made longer. The signal charge transfer time from the electrodeHSL to the horizontal transfer path 56 may then be made longer, sincethe signal charge is transferred from the electrode HL to the horizontaltransfer path 56 during the high level time of the drive signal φHP1.Moreover, if the period of the drive signal φHP is changed to a longerperiod, the time during which the drive signal φHL is low in level andthe drive signal φHP1 is high in level may be made longer, even in casethe duty cycle is 50%, whereby it is possible to provide for longersignal charge transfer time from the electrode HL to the electrode HSL.

In particular, if the duty cycle of the drive signal φHL is alsochanged, as in the present alternative embodiment, the time during whichthe drive signal φHL is low in level and the drive signal φHP1 is highin level may be made longer, whereby it is possible to provide forlonger signal charge transfer time from the electrode HL to theelectrode HSL. Meanwhile, whether or not the duty cycle is to be changedwhen the period of the drive signal φHL is changed may optionally bedetermined depending on the state of transfer then prevailing in thetransfer section.

When the duty cycle of the drive signals φHP1 and φHP2 is changed, thetransfer time from the electrode HSL to the horizontal transfer path 58becomes shorter from Te to Tq (time Te>time tq). It is noted that, incase the signal charges of the pixels R and B are being transferred tothe horizontal transfer path 56 and the signal charges of the pixel Gare being transferred to the horizontal transfer path 58, as in thepresent alternative embodiment, the signal charge of the pixel G tendsto be mixed into those of the pixels R and B, since the transfer timefrom the branching section to the horizontal transfer path 58 becomesshorter. However, since the signal quantities of the pixels R and Bdiffer from each other, the adverse effect of mixing of signal charges,if any, is only small.

In case the duty cycle of the drive signals φHP1 and φHP2 is changed asshown in FIG. 43, the reset level Tr and the feed-through level Ts ofthe output waveforms OS1, OS2 become shorter, and the data level Ttbecomes longer. Thus, in case the noise is removed in the rear sidepre-processor 22 in accordance with the correlated double sampling, itbecomes necessary to change the phase of the sampling pulse in keepingwith the change in the drive signals φHP1 and φHP2.

In the present alternative embodiment described above, the duty cycle orthe period of the drive signals φHL, φHP1 and φHP2 is changed to providefor longer transfer time from the electrode HL towards the electrode HSLor longer transfer time from the electrode HSL towards the horizontaltransfer path 56 to provide for transfer of a sufficient quantity ofsignal charges, as shown in FIGS. 44 and 45. Consequently, the transferefficiency may be prevented from being deteriorated in the electrodeHSL. In addition, since the duty cycle or the period may be changed bychanging the timing signal generated by the timing signal generator 32shown for example in FIG. 2, it is possible to prevent deterioration ofthe transfer efficiency without requiring redundant elements.

The above-described driving with variable duty cycle or period of thedrive signals φHL, φHP1 and φHP2 for eliminating the deterioration oftransfer deterioration may be effected depending on, for example, thetemperature of the device 44, color temperature of the subject, ISO(International Organization for Standardization) sensitivity or thedriving speed. For example, the transfer efficiency tends to bedeteriorated under low temperature in the device 44. This deteriorationmay be coped with by driving with variable duty cycle or period.

Meanwhile, the temperature of the device 44 may be measured by knowntemperature measurement means, such as a thermometer or a sensor, asmounted in an optional location of the solid state imaging apparatus,such as in the imaging unit 14 or in the system controller 28. If themeasured temperature is lower than a preset value, the timing signalgenerator 32 may be controlled by, for example, the system controller28, in order to change the duty cycle or the period of each drivesignal, whereby it becomes possible to prevent deterioration of thetransfer efficiency under low temperatures, only by way of example.

Meanwhile, if the detected temperature is higher than a preset value,the transfer efficiency becomes higher. Hence, usual driving ispreferably used. Specifically, with a high detected temperature, thetiming signal generator 32 routes to the drivers a usual timing signalin which the duty cycle is 50%, with the low level time and the highlevel time each being one-half period.

In case the color temperature is drastically high or low, an ill effectcaused by mixing of the signal charges of the pixel R and the pixel Binto those of the pixel G is increased. The duty cycle or the period maythen be changed to eliminate transfer deterioration to combat the illeffect caused by mixing.

The color temperature may be said to be drastically high in case it ishigher than 6000 Kelvin, as an example. The color temperature may besaid to be drastically low in case it is lower than 3000 Kelvin, as anexample. The present invention is not limited to these numerical values.The color temperature may be detected using known techniques.

In driving at high ISO sensitivity, that is, in case the imaging opticalsensitivity is higher than the usual imaging sensitivity, the subject islow in luminance and hence the quantity of signals generated may be low.Hence, the ill effect caused by mixing tends to be increased, the dutycycle or the period may then be changed to eliminate transferdeterioration to combat the ill effect caused by mixing.

During high speed driving, the transfer time becomes shorter than duringusual driving. Hence, it is feared that the quantity of signal chargesleft over is increased. Thus, by varying the duty cycle or the periodfor driving, it becomes possible to prevent mixing to generate anoptimum image. Meanwhile, during the low speed driving, it is preferredto revert to usual driving, because sufficient transfer time may then besecured. However, the present invention is not limited to these cases.The duty cycle or the period may be changed in an optional case wherethere is fear of deterioration in the transfer efficiency in thebranching section 54, in order to eliminate deterioration.

In the processing shown in FIGS. 44 and 45, it is possible to freely sethow much the duty cycle is to be changed. That is, the range ofvariations of the duty cycle may be set freely. This setting may be madeby measuring, in a situation where deterioration in the transferefficiency is likely to be produced, the quantity of signal chargeswhich may be left over to the rear side, and by calculating the transferefficiency using the so measured quantity of signal charges left over tothe rear side.

FIG. 44 is a flow chart showing typical processing of calculating thetransfer efficiency, by measuring the residual transfer quantity, forsetting the magnitude of variation of the duty cycle. In FIG. 44, thesystem controller 28 captures a light source of a predetermined lightvolume in the imaging unit 14 to generate a reference signal (step S1).Under such control, the imaging unit 14 shoots the light source of apredetermined light volume and, as shown in FIGS. 31 to 34, mixes eightpixels in the horizontal direction on the horizontal transfer path 50 togenerate a reference signal pixel 400 and at least three void pixels 402to 406 consecutive to the reference signal pixel on its rear side.Meanwhile, it is sufficient that there are at least two pixels on therear side of the pixel 400, so that the present alternative embodimentis merely an illustration and is not restrictive.

In case the reference signal pixel 400 and three consecutive void pixelsare generated in this manner in rear of the reference signal pixel 400,the branching section 54 of the device 44 bifurcates the referencesignal pixel 400 and the void pixels, so that the reference signal pixel400 and one of the three void pixels are supplied to one of thehorizontal transfer paths, and the remaining two void pixels aresupplied to the other horizontal transfer path (step S2).

FIG. 45 schematically shows how the reference signal pixel 400 and thethree consecutive void pixels in rear of the reference signal pixel 400,generated by the processing shown in FIGS. 31 to 34, are beingtransferred from the branching section 54 to the horizontal transferpaths 56 and 58. Specifically, FIG. 45 schematically shows the exemplaryprocessing for calculating the transfer efficiency. In FIG. 45, the samereference numerals as those of FIG. 35 denote the same component parts.In FIG. 45, the reference signal pixel 400 and void pixels 402, 404, 406are supplied from the horizontal transfer path 50 to the branchingsection 54. As a result of bifurcation at the branching section 54, thereference signal pixel 400 and the void pixel 404 are sequentiallysupplied to the horizontal transfer path 56. To the horizontal transferpath 58, the void pixel 402 directly in rear of the reference signalpixel 400 on the horizontal transfer path 50, and the void pixel 406 aresequentially supplied.

The reference signal pixel 400 and the void signal 404 are sequentiallytransferred on the horizontal transfer path 56, to the output amplifier60 which then outputs the signal 82 composed of the reference signalpixel 400 and the void signal 404. In similar manner, the void pixels402, 406 are sequentially transferred on the horizontal transfer path 58to the output amplifier 62 which then outputs the signal 84 composed ofthe void pixels 402, 406. The signals 82, 84 are then processed by thepre-processor 22 to generate digital signals 110, 112, which are thenstored in the memory 24.

At the time of branching to the horizontal transfer path 56 from thebranching section 54, if there are left-over signal charges, theseleft-over signal charges are admitted into the branched void pixel 402.The signal processor 26 reads out the reference signal pixel 400 and thevoid pixel 402 from the memory 24, as digital signal 118, over bus 114and signal line 120, and calculates the transfer efficiency HTR_(HSL1)at the time of transfer from the branching section 54 to the horizontaltransfer path 56, in accordance with the expression (1) (step S3):

$\begin{matrix}\frac{\left( {S - T} \right) \times 100}{S} & (1)\end{matrix}$

where S denotes the signal quantity of the pixel 400, T the quantity ofleft-over signal charges detected from the void pixel 402, that is, thequantity of residual signal charges. Meanwhile, the present invention isnot limited to this processing. The invention can deal with any pixel.

After branching, signal charges left over to the rear side on thehorizontal transfer path 56 are admitted into the void pixel 404. Thus,in the present alternative embodiment, the signal processor 26 detectsthe quantity of residual signal charges present in the void pixel 404 tocalculate the transfer efficiency HTR_(OS1) (step S4). It is similarlypossible to calculate the transfer efficiency HTR_(OS1) by setting thequantity of residual signal charges detected from the void pixel 404, asthe variable T in the above expression (1). In particular, the residualcharges left over in the ultimate stage on the horizontal transfer path56, that is, between the output gate and the floating diffusionamplifier shown in FIG. 36 are admitted into the void pixel 404. It istherefore useful in improving the ill effect, such as imagedeterioration, to maintain the transfer efficiency calculated with theuse of the void pixel 404.

In this manner, the transfer efficiency in branching from the branchingsection 54 to the horizontal transfer path 56 and the transferefficiency on the horizontal transfer path 56 are calculated. Thetransfer efficiency HTR_(HSL2) and the transfer efficiency HTR_(OS2) onthe horizontal transfer path 58 may similarly be calculated as shown inFIG. 46. Specifically, the transfer efficiency HTR_(OS2) on thehorizontal transfer path 58 may be calculated by supplying the referencesignal pixel 400, prepared by the processing of FIGS. 31 through 32I, tothe horizontal transfer path 58, and by subsequently detecting signalcharges present in the void pixel 404, as shown in FIG. 46. The transferefficiency HTR_(HSL2) in branching signal charges from the branchingsection 54 to the horizontal transfer path 58 may also be calculated bydetecting the signal charges present in the void pixel 404.

The transfer efficiency calculated may be that for the reference signalpixel 400 of a preset signal quantity, as an example. However, since theresidual charge quantity is varied with the signal quantity of thereference signal pixel 400 as shown in FIGS. 47 and 48, it is alsopossible to provide several reference signal pixels 400 of differentsignal quantities and to calculate the transfer efficiency from onesignal quantity to another. It is noted that the present invention isnot limited to calculating the transfer efficiency by the techniqueshown in FIGS. 46 to 48 and any suitable known technique may also beused.

FIG. 47 schematically shows measured results of the residual chargequantity for different signal quantities of the reference signal pixel400. FIG. 48 schematically shows a transfer efficiency calculated fromthe residual charge quantity as shown in FIG. 47. In FIG. 47, theabscissa and the ordinate represent the signal quantity (mV) of thereference signal pixel 400 and the residual charge quantity (mV),respectively. FIG. 47 shows the results of detection of the residualsignal charges in the branching section 54. In this figure, a curve 232stands for residual charges on bifurcating signal charges from thebranching section 54 to the horizontal transfer path 56, that is, thesignal quantity detected from the void pixel 402 of FIG. 45. Anothercurve 234 stands for residual charges on bifurcating signal charges fromthe branching section 54 to the horizontal transfer path 58, that is,the signal quantity detected from the void pixel 402 of FIG. 46. On theother hand, there are shown in FIG. 48 the transfer efficiencyHTR_(HSL1) and the transfer efficiency HTR_(HSL2) as calculated from therespective values shown in FIG. 47. The present invention is not limitedto calculating the transfer efficiency at the branching section 54. Thatis, the transfer efficiencies in the horizontal transfer paths 56 and 58may similarly be calculated from one signal quantity of the referencesignal pixel 400 to another.

FIG. 49 is a flowchart showing exemplary processing for calculating thetransfer efficiency by the solid state imaging apparatus 10 inaccordance with the sequence shown in FIG. 44 and for setting variablevalues of the duty cycle with the use of the so calculated transferefficiency. In FIG. 49, the transfer efficiency of a section, for whichare set the variable values of the duty cycle or the period, iscalculated in accordance with the sequence shown in FIG. 44 for settingthe variable values (step S11). For example, in determining the variablevalues used in increasing the transfer time from the branching section54 to the horizontal transfer path 56, in the present alternativeembodiment, a reference signal pixel 400 of a certain signal quantity isgenerated, and the transfer efficiency HTR_(HSL1) and the transferefficiency HTR_(HSL2) are calculated as shown in FIG. 48.

Meanwhile, the transfer efficiency calculated at this time is used as areference in setting the variable values. Thus, in calculating thetransfer efficiency at the step S11, it is preferred to set the dutycycle of each of the drive signals φHL, φHP1 and φHP2 to 50% and to seta constant period, for usual driving. However, this is not meant forrestricting the present invention.

Once the transfer efficiencies in bifurcating the signal charges fromthe branching section 54 to the horizontal transfer paths 56 and 58 areobtained, it is verified whether or not one of the transfer efficienciesexceeds a reference value (step S12). For example, in the presentalternative embodiment, it is verified whether or not the transferefficiency HTR_(HSL1) of the horizontal transfer path 56 exceeds thereference value.

For the reference value, an optionally set value may be used. Forexample, it may be set based on the transfer efficiencies HTR_(HSL1) orHTR_(HSL2″) as calculated in the step S11, or may be empirically set.However, this is not meant to restrict the present invention. Forexample, in the present alternative embodiment, the reference values areset as indicated by dotted lines 242, 244 in FIG. 48. In this figure,the dotted line 242 is a reference value of the transfer efficiency inbranching from the branching section 54 to the horizontal transfer path56, while the dotted line 244 is a reference value of the transferefficiency in branching from the branching section 54 to the horizontaltransfer path 58.

It is noted that an image generated is affected severely by transferdeterioration that should occur in branching from the branching section54 to the horizontal transfer path 56. Thus, in the present alternativeembodiment, the reference value of the transfer efficiency in branchingfrom the branching section 54 to the horizontal transfer path 56 is setmore severely than that in branching from the branching section 54 tothe horizontal transfer path 58. The present invention is not limited tothis and the same reference value may be set for branching from thebranching section 54 to the horizontal transfer path 56 and forbranching from the branching section 54 to the horizontal transfer path58.

As a result of decision in the step S12, if the transfer efficiencyHTR_(HSL1) is higher than the reference value, processing transfers to astep S13 in order to verify whether or not the other transferefficiency, specifically the transfer efficiency HTR_(HLS2), forbranching from the branching section 54 to the horizontal transfer path58 exceeds the transfer efficiency (step S13).

As a result of decision in the step S13, if the transfer efficiencyHTR_(HSL2) also exceeds the reference value, the processing for settingthe variable value is finished. If the result of decision in the stepS13 indicates that the transfer efficiency HTR_(HSL2) is lower than thereference value, the duty cycle or the period of each drive signal isadjusted (step S14). Specifically, the duty cycle or the period of eachdrive signal is adjusted. It may optionally be set how much the dutycycle or the period is to be changed. For example, the duty cycle or theperiod may be set depending on how much the transfer efficiencyHTR_(HSL1) exceeds the reference value, or on how much the transferefficiency HTR_(HSL2) falls below the reference value. The duty cycle orthe period may also be set as the amount of change for each adjustmentevent, for example, the value of increase of the duty cycle, such as 5%,is set and the adjustment is then made based on this change amount.However, this is not meant for restricting the present invention.

After the adjustment in the step S14, processing reverts to the step S11to calculate the transfer efficiencies HTR_(HSL1), HTR_(HSL2) again. Itis then verified whether or not the transfer efficiencies HTR_(HSL1),HTR_(HSL2) exceed the reference values. If the transfer efficienciesHTR_(HSL1), HTR_(HSL2) exceed the reference values, processing isterminated. Why the processing reverts to the step S11 is to verifywhether or not the transfer efficiency HTR_(HSL2) in switching from thebranching section 54 to the horizontal transfer path 58 has beenimproved, and also is to verify whether or not the transfer efficiencyHTR_(HSL1) in switching from the branching section 54 to the horizontaltransfer path 56 has become lower than the reference value as a resultof change in the duty cycle or the period in the step S14.

As a result of decision in the step S12, if the transfer efficienciesHTR_(HSL1) has become lower than the reference value, processingtransfers to a step S15 to verify whether or not the other transferefficiency HTR_(HSL2) has exceeded the reference value (step S15). Ifthe result of decision indicates that the other transfer efficiencyHTR_(HSL2) has also become lower than the reference value, it isdetermined that the variable value cannot be set (step S16) to terminatethe processing.

If the transfer efficiency HTR_(HSL2) has exceeded the reference value,the duty cycle or the period of each drive signal is adjusted so thatthe transfer efficiency HTR_(HSL1) will become higher (step S17). Howmuch the duty cycle or the period is to be changed may optionally beset, as in the step S14. After the change, processing reverts to thestep S11 to verify how much the transfer efficiency HTR_(HSL1) has beenimproved by the change in the step S17, and whether or not the othertransfer efficiency HTR_(HSL2) has become lower than the referencevalue.

The variable value is set as the transfer efficiencies HTR_(HSL1),HTR_(HSL2) are measured, as described above. It is therefore possible inthis manner to avoid the problem that, while the transfer efficiency onone of the horizontal transfer paths may be improved as a result ofchanges in the duty cycle or the period, the transfer efficiency on theopposite side horizontal transfer path is deteriorated, so that it ispossible to obtain the variable value which may be optimum case by case.Although it is the variable value in branching from the branchingsection 54 to the horizontal transfer paths 56, 58 that is set in thepresent alternative embodiment, it is possible to set the variable valuein changing the transfer time from the electrode HL before branching tothe electrode HSL of the branching section 54 in similar manner.

The variable values may preferably be set under a condition which mayaggravate the transfer efficiency, such as at elevated temperatures,higher sensitivity, high speed readout or at an extremely high orextremely low color temperature, since it is then possible to obtain thevariable value which will improve transfer deterioration moreeffectively. It is also preferred to calculate the transfer efficiencyor set the variable values at the time of shipment of the device 44 orthe solid state imaging apparatus 10 since then it is possible to takeup individual differences of the solid state imaging apparatus 10 fromone solid state imaging apparatus to another. Of course, the presentinvention is not limited to this and the variable values may be setunder optional conditions and at optional stages.

A further alternative embodiment of the present invention will now bedescribed. FIG. 50 shows an alternative embodiment of the device 44according to the present invention. In case signal charges for pluralcolors are transferred on the horizontal transfer path 50, the signalcharges are bifurcated by the branching section 54 from color to color,to each of the plural horizontal transfer paths 56 and 58, and analogvoltage signals 82, 84 converted from the signal charges are outputsimultaneously. In case signal charges for one color are transferred onthe horizontal transfer path 50, the analog voltage signal 82 convertedfrom the signal charges are output from the selected horizontal transferpath 56, as an example.

In the present alternative embodiment, the color filter separates theincident light into three colors of red, green and blue. The threecolors are divided into a group consisting of red and blue, and anothergroup consisting of green. Of the three colors of red, green and blueconstituting a line, green is read out separately from the red and blue.Then, of the three colors of red, green and blue constituting the nextline, green is read out separately from the red and blue. This operationis repeated for all lines making up the entire pixels (one frame). Thatis, the readout system is progressive.

The signal charges for green color read out from the photosensitivecells are transferred by using only the horizontal transfer path 56. Thesignal charges for red and blue colors read out from the photosensitivecells are transferred by using the horizontal transfer paths 56 and 58.The red color and the blue color are transferred over the horizontaltransfer paths 56 and 58, respectively.

The digital camera 10 includes the optical system 12, the imaging unit14, amplifier power supply 16, biasing circuit 18, drivers 20,pre-processor 22, memory 24, signal processor 26, system controller 28and timing signal generator 32 as shown in FIG. 50.

The branching section 54 is supplied from the biasing circuit 18 with abias signal 72 as a fixed voltage. The branching section 54 causessignal charges from the horizontal transfer path 50 to be branched toone of the horizontal transfer paths 56 and 58, depending on the colors,in a manner which will be described later.

The HS driver 96 outputs the horizontal drive signal 74 to the device44. The HP driver 98 outputs the horizontal drive signal 76 to thedevice 44. The horizontal drive signal 76 has a period equal to or twicethe period of the horizontal drive signal 74, depending on which coloris being transferred. In the present alternative embodiment, the periodof the horizontal drive signal 76 is constant, and the period of thehorizontal drive signal 74 is equal to or half the period of thehorizontal drive signal 76, depending on the colors. The RS driver 100outputs the reset signal 68 and 70 to the device 44.

The signal processor 26 has the function of performing signal processingon the digital signal 118 supplied to generate a control signal. Thesignal processor 26 includes the power supply control 122 and the biascontrol 124. The signal processor 26 shown in FIG. 50, of course,includes those components corresponding to the AF control 126, AEcontrol 128, AWB control 130 and data converter 132 shown in anddescribed with reference to FIGS. 2 and 23, which are not shown merelyfor the purpose of simplicity. The power supply control 122 has thefunction of generating the control signal 86 responsive to high speedreadout or low speed readout. The power supply control 122 outputs thecontrol signal 86 generated to the amplifier power supply 16.

The bias control 124 outputs the control signal 88 to the biasingcircuit 18. The biasing circuit 18 applies the bias signal 72 to thebranching section 54.

The constitution of the horizontal transfer path 50, the branchingsection 54 and the horizontal transfer paths 56 and 58, and the methodfor horizontal transfer of signal charges will now be described. Thefollowing description will be made separately for transfer on thebranching section 54 and the horizontal transfer path 56 and fortransfer on the branching section 54 and the horizontal transfer path58. There are provided plural transfer elements as described above, oneach of the horizontal transfer paths 50, 56 and 58. In the following,the sole transfer element and the two electrodes contained therein aredenoted by the same reference numeral. For example, the ‘branchingsection 54’ denotes a transfer element, and the ‘electrode 54’ denotestwo electrodes of the branching section 54.

On the horizontal transfer path 50, there are formed polysiliconelectrodes HS2 and HS1, in this order, from right to left, towards thebranching section 54 (electrode HSL), as shown in FIG. 51. This set ofthe polysilicon electrodes constitutes a repetitive unit. On thehorizontal transfer path 56, there are provided six polysiliconelectrodes HP1, HP2, HP1, HP2, HP1, HP2, from the branching section 54towards the output amplifier 60. On the horizontal transfer path 58,there are provided seven polysilicon electrodes HP2, HP1, HP2, HP1, HP2,HP1, HP2, from the branching section 54 towards the output amplifier 62.The horizontal transfer paths 56 and 58 are of the same structure as inFIGS. 4 and 7, as may be understood from FIGS. 51 and 52.

The drive signals applied to the respective electrodes will now bedescribed. The drive signals φHS1 and φHS2 are supplied to theelectrodes HS1 and HS2, respectively. The drive signal φHSL is suppliedto the electrode HSL. The drive signal φHSL is a constant bias voltage.The drive signals φHP1 and φHP2 are supplied to the electrodes HP1 andP2, respectively. A drive signal φOG is supplied to the electrode OG.The drive signal φOG is a constant bias voltage. The drive signal φRS issupplied to the reset drain RS. The drive signal φRS is a constant biasvoltage.

The flow of signal charges, transferred horizontally by these drivesignals, inclusive of vertical transfer preceding horizontal transfer,will now be described. Initially, the signal charges are generated inthe device 44 of the imaging unit 14. The array of pixels in the device44 is shown in FIG. 53. In the device 44 of the present alternativeembodiment, shown in FIG. 53, the filter array is generally of theso-called G-square RB-complete checkered pattern.

The charge transfer sequence on the vertical transfer path 48 is lines201, 252, 203 and 254. On the line 201, the signal charges are arrayedin the order of R, B, R, B, . . . . On the lines 252, 254, the signalcharges are arrayed in the order of G, G, G, G, . . . . On the line 203,the signal charges are arrayed in the order of B, R, B, R, . . . . Thissequence is maintained on the horizontal transfer paths 50, 56 and 58,so that the signal charges are transferred in the sequence of R, B, R,B, . . . of line 201, G, G, G, G, . . . of line 252, B, R, B, R, . . .of line 203 and G, G, G, G, . . . of line 254.

It is noted that R, B, R, B, . . . on the line 201 and B, R, B, R, . . .on the line 203 are transferred on the two horizontal transfer paths 56and 58, while G, G, G, G, . . . on the lines 252, 254 are transferred onthe sole horizontal transfer path 56. Moreover, as regards the R, B, R,B, . . . on the line 201 and B, R, B, R, . . . on the line 203, theseare separated into R and B signals, by the branching section 54, so thatthe R signals and B signals are transferred at all times on thehorizontal transfer paths 56 and 58, respectively.

This is shown in FIGS. 54A through 55E. FIGS. 54A through 54E show howthe R, B, R, B, . . . on the line 201 and B, R, B, R, . . . on the line203 are transferred horizontally at times t=1, 2, 3, 4 and 5. FIGS. 55Athrough 55E show how the G, G, G, G, . . . on the lines 252, 254,transferred next to lines 201 and 203, respectively, are transferredhorizontally at times t=1, 2, 3, 4 and 5. The times t=1, 2, 3, 4 and 5are those at which signal charges are transferred on the horizontaltransfer path 50 towards left by one transfer element at a time. Sincethe horizontal transfer paths 56 and 58 are driven in FIG. 54 at afrequency equal to one-half that for the horizontal transfer path 50,the transfer speed on the horizontal transfer paths 56 and 58 isone-half that on the horizontal transfer path 50. On the other hand, thehorizontal transfer paths 56 and 58 are driven in FIG. 55 at a frequencyequal to that for the horizontal transfer path 50, and the transferspeed on the horizontal transfer paths 56 and 58 is equal to that on thehorizontal transfer path 50. The method for implementing this will bedescribed in detail subsequently.

In the signal processor, next following the horizontal transfer paths,processing is carried out on the assumption that a first line is formedby signal charges on the lines 201 and 252 and that a second line isformed by signal charges on the lines 203 and 254. Meanwhile, RGBGRGBG .. . and BGRGBGRG . . . are stated as first and second lines on thehorizontal transfer path 50 shown in FIG. 51. This indicates in whichlocations on the horizontal transfer path 50 the signal charges descendin the drawing from the vertical transfer paths 48, but does notindicate that the signal charges are transferred in the sequence ofRGBGRGBG . . . and BGRGBGRG . . . on the horizontal transfer path 50.

Reverting to FIGS. 55A through 55E, the signal charges read out from thephotosensitive cells 46 to the vertical transfer path 48 are transferredon the vertical transfer path 48 towards the horizontal transfer path 50by eight-phase drive signals φV1 to φV8 supplied to the verticaltransfer path 48. On the horizontal transfer path 50, there are providedthe electrodes HS1, HS2, HS1, HS2, . . . are provided from its left end,as described previously.

With the honeycomb array and with G-square RB-complete checkeredpattern, as in the present alternative embodiment, the G signals and theRB signals descend on separate lines, that is, lines 201 and 252,respectively. However, with a routine array of photosensitive cells andthe color filter segments, the G signals and the RB signals do notnecessarily descend in separated states. In such case, it becomesnecessary to re-array the G signals and the RB signals. To this end, itis sufficient to provide a line memory between the vertical transferpath 48 and the horizontal transfer path 50 for re-arraying the signalsand subsequently transfer the re-arrayed signals to the horizontaltransfer path 50.

The drive signals on the horizontal transfer paths 50, 54, 56 and 58will now be described. Initially, the case of transferring R, B, R, B, .. . on the line 201 and B, R, B, R, . . . on the line 203 will bedescribed. FIG. 56 shows drive signals for transferring R, B, R, B, . .. on the lines 201 and 203. If attention is directed to the phase of thedrive signals, the drive signal φHS1 of FIG. 56, part (A), is a twophase drive signal phase-shifted by 180° from the drive signal φHS2 ofpart (B). The drive signal φHP1 of part (C) and the drive signal φHP2 ofpart (D) are phase-reversed from each other and are two phase drivesignals.

If attention is directed to the periods of the drive signals, the drivesignals of FIG. 56, parts (A) and (B) are each of a period equal toone-half the period of parts (C) and (D). That is, the frequency of eachof the drive signals of parts (A) and (B) is twice the frequency of eachof the drive signals of parts (C) and (D). The drive signal φRS as shownin part (E) becomes “H” in level at, e.g. the time t=1, . . . , t=5,that is at time t=4n+1, where n is an integer including zero. Outputsignals OS1 and OS2 are output as shown in part (F).

FIGS. 57A through 61B show the potential generated on the horizontaltransfer paths 50, 54, 56 and 58 in case the above drive signals areapplied to the horizontal transfer paths 50, 54, 56 and 58. Thosefigures also depict the structure shown in FIG. 52. A simplified diagramof FIG. 52 is also shown for indicating the potential positions. FIGS.57A and 57B are for time t=1 of FIG. 54A, FIGS. 58A and 58B are for timet=2 of FIG. 54B, and FIGS. 59A and 59B are for time t=3 of FIG. 54C.FIGS. 60A and 60B are for time t=4 of FIG. 54D, and FIGS. 60A and 61Bare for time t=5 of FIG. 54E. FIGS. 57A, 58A and 59A, and 60A and 61Astand for the horizontal transfer paths 50, 54 and 56. FIGS. 57B, 58Band 59B, and 60B and 61B stand for the horizontal transfer paths 50, 54and 58. Thus, as may be seen from the figures, the potential levels ofFIGS. 57A, 58A, 59A, 60A and 61A, and of FIGS. 57B, 58B, 59B, 60B and61B are the same insofar as the horizontal transfer paths 50 and 54 areconcerned.

Referring further to FIGS. 56 through 61B, horizontal transfer will bedescribed. Since the drive signal φHSL is supplied, in a manner notshown, there are generated a potential level of the reference level 146always fixed, and a potential level (barrier) 148 which prohibitsreverse flow of signal charges supplied from the horizontal transferpath 50, in a region directly below the electrode HSL supplied with thedrive signal φHSL.

The shifting of the signal charges by the variable potential levelsgenerated responsive to the drive signals supplied, and the constantpotential levels 146, 148 will now be described. The signal chargescorresponding to the colors R, G and B are referred to below as signalcharges R, G and B. Initially, the transfer of the signal charge R onthe horizontal transfer path 56 will be described with reference toFIGS. 57A, 58A, 59A, 60A and 61A.

The reason the signal charges may be distributed in the branchingsection 54 in the present alternative embodiment will now be described.There are provided impurity layers directly underneath the electrodesHP2 and HP1 of the horizontal transfer paths 56 and 58 next followingthe branching section 54. Thus, when the electrodes HP2 and HP1 aresupplied with the level “H”, there are generated stepped potentiallevels, that is, a level lower by one step than the reference level 146and the deepest level. The reference level 146 is generated at all timesin the branching section 54 by the constant bias voltage. This is shownfor example in FIG. 57B. When the electrodes HP2 and HP1 are suppliedwith the level “L”, there are generated a potential level higher by onestep than the reference level 146 and a potential level which is thesame as the reference level 146. This is shown for example in FIG. 57A.Hence, the potential level generated is sequentially lowered in stepsalong the signal charge transfer direction. Based on the above, theoperation with lapse of time will now be described.

At time t=1 in FIG. 56, the drive signals φ1, φHS2, φHSL and φHP1 aresupplied. The drive signals φHS2 and φHP1 are “L” in level. In case thedrive signals are supplied in this manner, the signal charge B isretained in the branching section 54. At this time, there is generated,in the impurity layer directly underneath the electrode HP1 of thehorizontal transfer path 56 neighboring to the electrode HSL, by theabove supply of the level “L”, a potential level 148 or a barrier whichis just enough to prevent the signal charge B from mixing into thehorizontal transfer path 56.

The electrode HP2 on the horizontal transfer path 58, neighboring to thebranching section 54, is supplied with the potential level “H” of thedrive signal φHP2. By this, a potential level 152 lower than thereference level is generated as shown in FIG. 57B such as to permit thesignal charge B to flow into the horizontal transfer path 58. At thistime, the signal charge B is held in both packets of the reference level146 and the potential level 152. At time t=1, signal charges R areretained at every other electrode on the horizontal transfer path 56.

Then, at time t=2 in FIG. 54B, a drive signal φHS2 at level “H” isapplied to the electrode HS2 on the horizontal transfer path 52. Withthe drive signal, thus applied, there are generated the potential level148 and the reference level 146 below the electrode HS2. With thesepotential levels applied, a packet is generated between the electrodesHS2 and HSL. In this packet is retained the signal charge R. To theelectrodes of the horizontal transfer paths 56 and 58 are supplied drivesignals of the same level as that at time t=1. Hence, the potentiallevels generated is not changed as from time t=1. In the interim, thesignal charge B is shifted from the electrode HSL to the electrode HP2on the horizontal transfer path 58, as shown in FIG. 58B.

Then, at time t=3 in FIG. 54C, there is generated the drive signal φHS2at level “L” at the electrode HS2. By this drive signal applied, thepotential level is as shown at time t=1. By this potential level, thesignal charge R retained in the packet generated at the electrode HS2 attime t=2 is moved to the reference level 146 of the branching section54, as shown in FIG. 59A. At this time, the level “H” drive signal φHP1is supplied to the electrode HP1 of the horizontal transfer path 56neighboring to the electrode HSL. The potential level generatedunderneath the electrode HP1 is a low level 152 which is lower than thereference level 146. As a result, the signal charge R is held in bothpackets of the reference level 146 and the potential level 152. At thistime, the level “L” drive signal φHP2 is supplied to the electrode HP2on the horizontal transfer path 58. Hence, a potential level 148 isgenerated at the electrode HP2, as shown in FIG. 59B. This potentiallevel 148 prohibits the signal charge R from mixing into the horizontaltransfer path 58. The signal charge R of the branching section 54 ismoved towards the packet generated at the electrode HP1 on thehorizontal transfer path 56, as shown in FIG. 59A.

The level “L” drive signal φHP2 is supplied to the electrode HP2 on thehorizontal transfer path 58 neighboring to the electrode HSL, asdescribed above. Thus, the potential level 148 and the reference level146 are generated below the electrode HP2, while the level “H” drivesignal φHP1 is applied to the electrode HP1 neighboring to the electrodeHP2. This generates a potential level one step lower than the referencelevel 146 and the deepest potential level below the electrode HP1. Inaddition, the potential level 148 and the potential level of thereference level 146 are generated by the potential level “L” supplied tothe neighboring electrode HP2. As a result, the signal charge B retainedby the packet at time t=2 is moved to and retained by the packetgenerated at the electrode HP1.

The signal charges R, B at the electrode HP2 retained in a packetgenerated just in rear of the output parts 60, 62 of the horizontaltransfer paths 56, 58, at time t=2, are moved towards the output sidewith rise in the potential level, and transferred via electrode OG tothe section FD.

Then, at time t=4, the level “H” drive signal φHS2 is supplied to theelectrode HS2, so that there is generated a potential which is the sameas that at time t=2. The signal charge B is retained in the packetgenerated at this time. The signal charge Rat the branching section 54is moved to the packet formed directly below the electrode HP1 of thehorizontal transfer path 56. The downstream side electrodes on thehorizontal transfer paths 56 and 58 are supplied with drive signals ofthe same level as that at time t=3. Hence, the potential levelsgenerated are the same as those at time t=3.

Then, at time t=5, the same potential as that at time t=1 is generatedat the impurity layer in register with the electrode HS2. This generatesa potential level 148 directly below the HP1 neighboring to thebranching section 54. The potential level 148 thus generated proves apotential barrier against the signal charge B. This signal charge B maybe prohibited from mixing into the horizontal transfer path 56. Thebranching section 54 shifts the signal charge 148 transferred theretofurther to the horizontal transfer path 58, as the branching sectiongenerates a packet. The drive signal of the same level as that at timet=1 is supplied to the horizontal transfer path 56. Hence, the potentiallevel generated is the same as that at time t=1. At time t=5, the signalcharges R, B supplied to the section FD are converted into analogvoltage signals, which are then output to the output amplifier 60.

The transfer on the horizontal transfer path 58 will now be described.On the horizontal transfer path 58, there are formed a plural number ofimpurity layers, directly underneath the respective electrodes on aP-type substrate, in the same way as on the horizontal transfer path 56.The impurity layers are obtained on partitioning a sole impurity layerin keeping with the sizes of the electrodes of polycrystalline silicon.Each of the impurity layer has the impurity concentration adjusted, forgenerating preset potential levels as later described, in keeping withthe voltage levels of the drive signals applied. The horizontal transferpath 58 is featured by having one more electrode than the number of theelectrodes on the horizontal transfer path 56.

At time t=1, the level “H” drive signal φHP2, the drive signal φHSL ofthe low bias voltage and the level “L” drive signal φHP1 are supplied toeach of the electrodes on the horizontal transfer path 58 as shown inFIG. 54A. With these drive signal applied, the signal charge B isretained at the branching section 54. With the drive signal φHP2applied, the potential level at the impurity layer of the electrode HP2on the horizontal transfer path 58 neighboring to the electrode HSL is alevel 152 one step lower than the reference level 146. The potentiallevel 148 generated below the electrode HP1 of the horizontal transferpath 56 operates as a potential barrier and prohibits mixing of thesignal charge B.

Since the level “L” drive signals φHP1 is supplied to the electrode HP1,there are generated the potential level 148 and the potential level ofthe reference level 146 directly below the electrode HP1. The level “H”drive signals φHP2 is supplied to the electrode HP2. This generates apotential level one step lower than the reference level 146 and apotential level of the lowest level directly below the electrode HP2.

At time t=1, when the drive signals are generated as described above,there are generated packets directly below the respective electrodesHP2. The signal charges B are retained in these packets.

Then, at time t=2, the level “H” drive signal φHS2 is applied to theelectrode HS2, as shown in FIG. 54B. With the drive signal applied,there is generated a potential level in the impurity layer below theelectrode HS2, as shown in FIGS. 58A and 58B, to generate a packet. Inthis packet is retained the signal charge R. The drive signals of thesame level as that at time t=1 are supplied to the further downstreamside electrodes on the horizontal transfer path 58. Hence, the potentiallevels generated are the same as those at time t=1.

FIG. 59B shows the potential at time t=3. The level “L” drive signalφHS2 is applied at this time t=3 to the electrode HS2. With the drivesignal applied, the potential level is as at time t=1. The signal chargeR retained by a packet directly underneath the electrode HS2 at time t=2is moved to the branching section 54 which is at reference level 146. Atthis time, the level “L” drive signal φHP2 is supplied to the electrodeHP2 on the horizontal transfer path 58 neighboring to the electrode HSL.The potential level of the impurity layer underneath the electrode HP2becomes a potential level 148 which is higher than the reference level146. That is, a potential barrier is generated. With the barrierproduced, the signal charge R is not mixed into the horizontal transferpath 58. On the other hand, a potential level 152 is generated by thelevel “H” supplied to the electrode HP1 on the horizontal transfer path56. This shifts the signal charge R as indicated by an arrow 162.Directly below the electrode HP1 on the horizontal transfer path 56supplied with the drive signal φHP1, there is generated a packet by thepotential level 152 as shown in FIG. 59A.

On the horizontal transfer path 58, there is generated a packet belowthe electrode HP1, at time t=3, by the level “H” supplied to the drivesignal φHP1. The signal charge B is retained by the packet at theelectrode HP1. With rise in the potential, the signal charge B retainedby the packet, generated at time t2, is moved towards the output sideand transferred towards the section FD via electrode OG.

Then, at time t=4, the same potential as that at t=2 is generateddirectly underneath the electrode HS2. The signal charge B is retainedin a packet generated at this time. The drive signals of the same levelas that at time t=3 are supplied to further downstream side electrodeson the horizontal transfer path 58. Thus, the potential levels generatedare of the same level as those at time t=3. The potential levelgenerated directly underneath the electrode HP2 neighboring to theelectrode HSL is in the state of the potential level 148 which is higherthan the reference level 146. The potential level generated directlyunderneath the electrode HP1 neighboring to the electrode HSL is in thestate of the potential level 152 which is lower than the reference level146.

Then, at time t=5, the same potential as that at time t=1 is generated.The signal charge B is retained in a packet of the electrode HP2. Thehorizontal transfer shown in FIG. 54 is achieved as described above. Thehorizontal transfer operation will now be described with reference toFIGS. 54A through 54E and further with reference to FIGS. 57A through58B.

In the horizontal transfer, the signal charges supplied at time t=1 fromthe horizontal transfer path 50 to the branching section 54, such as R,B, R, B, are distributed by the branching section 54 to the horizontaltransfer paths 56 or 58. As may be seen from FIGS. 54A through 54E, thesignal charges are retained at every other transfer element. Only thesignal charge R is transferred on the horizontal transfer path 56,responsive to the drive signal supplied. On the other hand, only thesignal charge B is transferred on the horizontal transfer path 58,responsive to the drive signal supplied. Since the potential barrierwall is generated at this time point at the electrode HP1 on thehorizontal transfer path 56 neighboring to the branching section 54, thesignal charge B is prevented from mixing into the horizontal transferpath 56.

The horizontal transfer path 50 is run at twice the frequency that ofthe horizontal transfer paths 56 and 58. Thus, at time t=2, the signalcharges held on the horizontal transfer path 50 are horizontallytransferred by one transfer element towards the branching section 54,responsive to the drive signals supplied. On the horizontal transferpath 56, no signal charge transfer occurs because the drive signalssupplied are not changed in level. On the horizontal transfer path 58,no signal charge transfer occurs as well because the drive signalssupplied are not changed in level. However, the signal charge B on thebranching section 54 is moved to the packet generated below theelectrode HP2 because the potential level, lower than the referencelevel 146 at the branching section 54, has been formed below theelectrode HP2.

At time t=3, the signal charges held on the horizontal transfer path 50are horizontally transferred by one transfer element towards thebranching section 54. The signal charges R are retained in the packetsformed on the branching section 54 and directly underneath theelectrodes HP1 on the horizontal transfer path 56 neighboring to thebranching section 54. At this time point, a potential barrier isgenerated at the electrode HP2 on the horizontal transfer path 58neighboring to the branching section 54. Hence, the signal charge R isprohibited from mixing into the horizontal transfer path 58. The signalcharges retained on the horizontal transfer paths 56 and 58, arehorizontally transferred towards the output sections 60, 62, each by onetransfer element, depending on the levels of the drive signals supplied.This sends the signal charges R and B to the output amplifiers 60 and 62on the horizontal transfer paths 56 and 58.

Then, at time t=4, the signal charges retained on the horizontaltransfer path 50 are horizontally transferred, each by one transferelement, towards the branching section 54, depending on the drivesignals supplied. The signal charge R is moved to the packet generateddirectly below the electrode HP1 on the horizontal transfer path 56neighboring to the branching section 54.

Then, at time t=4, the signal charges, held on the horizontal transferpath 50, are horizontally transferred, each by one transfer element,towards the branching section 54, depending on the drive signalssupplied. The signal charge R is moved to the packet, generated directlyunderneath the electrode HP1 of the horizontal transfer path 56neighboring to the branching section 54.

At time t=5, the signal charges held on the horizontal transfer paths50, 56 and 58 are horizontally transferred towards the output side, eachby one transfer element. The signal charges of the colors R and B arethen transformed simultaneously into corresponding analog voltagesignals, so as to be output as output signals OS1 and OS2 from theoutput amplifiers 60 and 62, respectively. These output signals OS1 andOS2 are processed by completely parallel processing. This eliminatesdifferential signal intensities attributable to processing in the timedomain of the output signals OS1 and OS2. Meanwhile, in case thedifferential signal intensities attributable to processing in the timedomain are tolerable, the output signals OS1 and OS2 may be outputalternately.

By the above processing, the signal charges may be transferred andoutput without mixing. In general, in keeping with increasing numbers ofpixels, it is required of a solid state imaging device to read out thesignal charges at a high speed. In order to meet this demand, it isnecessary to raise the frequency range of the output amplifiers on thehorizontal transfer paths. The solid state imaging device is difficultto drive at a frequency higher than a preset frequency. This is due forexample to shortage in the frequency band of the output amplifier. Withthe device 44 of the instant alternative embodiment, it is possible toread out output signal charges, from color to color, without thefrequency of the output amplifier increased, by bifurcating an outputand increasing the number of output channels, even though the drivingfrequency of the horizontal transfer path 50 is raised to cope with theincreasing number of pixels. That is, an improved signal charge readoutspeed may be achieved.

The drive signals on the horizontal transfer paths 50, 54, 56 and 58 fortransferring signal charges of the same color G, G, G, G, . . . on thelines 252 and 254 will now be described. For signal charges of the samecolor only the horizontal transfer path 56 out of the horizontaltransfer paths 56 and 58 is used in the present alternative embodiment.In this case, the drive signals φHS1 and φHS2 shown in FIG. 56, parts(A) and (B), are of the same frequency as the drive signals φHP1 andφHP2 shown in parts (C) and (D). That is, the drive signals φHS1 andφHS2 are lower in speed than in FIG. 56.

At time t=1, the drive signal φHS2 supplied to the last stage HS2 on thehorizontal transfer path 50 is “L”, while the drive signal φHP1 suppliedto the last stage HP1 is “H”, and drive signal φHP2 supplied to thefinal stage HP2 is “L”. Hence, the signal charge is transferred viabranching section (HSL) 54 to the electrode HP1, that is, to thehorizontal transfer path 56.

The potential levels generated on the horizontal transfer paths 50, 54,56 and 58, when the above drive signals are applied thereto, are shownin FIGS. 63A through 64B. FIGS. 63A through 64B show the structure shownin FIG. 52. A simplified form of FIG. 52 is also shown for indicatingthe potential positions. FIGS. 63A and 63B are for time t=1 of FIG. 62,and FIGS. 64A and 64B are for time t=2 of FIG. 62. FIGS. 63A and 64Astand for the horizontal transfer paths 50, 54 and 56, and FIGS. 63B and64B stand for the horizontal transfer paths 50, 54 and 58.

At time t=2, the drive signals φHS2 supplied to the last electrode HS2of the horizontal transfer path 50 is at level “H”. The drive signalsφHP1 supplied to the electrode HP1 is at level “L” and the drive signalφHP2 supplied to the electrode HP2 is at level “H”. Thus, the signalcharge is at the transfer element HS2. The signal charge is alsotransferred from the transfer element HP1 to the transfer element HP2.

The state at time t=3 is the same as that at time t=1, while the stateat time t=4 is the same as that at time t=2. The reason the states attime t=1 and those at time t=2 are repeated is that the drive signalsφHS1, φHS2, φHP1 and φHP2 are of the same frequency and the phaseadjustment has been made so that only the two states will be generated.

As for the output parts, the reset signal φRS shown in FIG. 62, part(E), is applied, while the output signals OS1, OS2 shown in FIG. 62,parts (F) and (G), are output. As for the transfer of the signal chargesG, the device 44 is in one-line outputting state for outputting only theoutput signal OS1, while the output signal OG2 is not used. Hence, thepower supply for the output amplifier 62 may be turned off. In thiscase, the power supply by the amplifier power supply 16 is controlled bythe control signal 86 from the power supply control 122 to turn off thepower supply 66.

It is also possible to reverse the phase of each of the drive signalsφHP1, φHP2, φHS1 and φHS2, in order to run only the output amplifier 62.By so doing, only the horizontal transfer path 58 may be run by way ofone-line outputting. Thus, in the instant alternative embodiment, it isreadily possible to switch between one-line outputting and two-lineoutputting or to freely select the output amplifiers.

If the sequence of R and B pixels in the first line and that in thesecond line are compared to each other, the sequence on the first line201 is R, B, R, B, while that on the second line 252 is B, R, B, R, asshown in FIG. 53. Thus, the first pixels of the lines differ from eachother. If the same horizontal transfer drive signals are used for thefirst and second lines, the pixels output from the output amplifier 60differ from line to line. The same may be said of the output amplifier62. The output amplifiers 60 and 62 slightly differ from each other incharacteristics, such as gain, so that step differences are produced atthe output stages for the same color. For avoiding this, the same coloris desirably output from the same output amplifier. The method forimplementing this will now be described.

The horizontal transfer drive signals for horizontal transfer on thelines 201, 203 of the first and second lines are shown in FIGS. 65 and66, respectively. Initially, the horizontal transfer on the line 201will be described with reference to FIG. 65. From the line 201, thesignal charges are transferred through the vertical transfer paths tothe horizontal transfer path 50, beginning from the line 201, in thesequence of the dummy pixels D1 and D2, optically black pixels OB1 andOB2, R, B, . . . .

The drive signals φHS1 and φHS2 shown in FIGS. 65 and 66 are supplied totransfer the signal charges held on the horizontal transfer path 50, tothe horizontal transfer paths 56 and 58. To these horizontal transferpaths 56 and 58, the drive signals φHP1 and φHP2 shown in FIG. 62, parts(C) and (D), are supplied. The transfer start position is such aposition where the potential of the drive signal is changed for thefirst time from the lapse of the horizontal blanking period 260. Inoutputting, the reset signal φRS shown in FIG. 62, part (E), is supplieddirectly before the signal charge is supplied to the output stage, andthe output signal is subsequently output in the output period 182.

The output stage converts signal charges into an analog voltage signal,and outputs the dummy D2, optical black OB2 and R, R . . . , in eachoutput time domain 182 as output signal OS1 of FIG. 62, part (F). Theoutput stage also outputs the dummy D1, optical black OB1 and B, B, . .. , in each output time domain 182 as output signal OS2 of FIG. 62, part(G). That is, the output signal OS1 on the horizontal transfer path 56outputs the color R, while the output signal OS2 on the horizontaltransfer path 58 outputs the color B.

On the other hand, in horizontally transferring the second line 203,outputting is switched to the first line 201. Hence, the drive signalsφHS1 and φHS2 shown in FIG. 66, parts (A) and (B), respectively, areused. The other signals are the same as those of the first line. On thesecond line, as compared to the first line, the start positions of thedrive signals φHS1 and φHS2 are faster by one period of these drivesignals.

Hence, the output stage outputs the dummy D1, the optical black signalOB1 and R, R in each output time domain 182, as output signal OS1 ofFIG. 66, part (F). The output stage also outputs the dummy D2, theoptical black signal OB2 and B, B . . . , in each output time domain182, as output signal OS2 of FIG. 66, part (G). In this manner, for thefirst and second lines, the same colors may be output from the sameoutput stages.

In the present alternative embodiment, the technique of phase-shiftingthe drive signal φHS is used. The present invention is not limited tothis and outputting may be to the horizontal transfer path 50 afterre-arraying employing a line memory. FIGS. 65 and 66 show a case wherethe drive signals φHS1 and φHS2 are fast. However, the same techniquemay be used in case the speed of the drive signals φHS1 and φHS2 is low.In either case, the output signals may be changed over extremelyreadily.

In FIGS. 55A through 55E, the signal charges G are transferred only onthe horizontal transfer path 50. Alternatively, the signal charges G mayalso be transferred using the horizontal transfer paths 56 and 58 asshown in FIGS. 67A through 67E. For the horizontal drive signals, it issufficient to use the signals shown in FIG. 56. In this case, high speedtransfer becomes possible with the signal charges G. However, since thesame color is output from the different output stages, step differencesfor the same color, attributable to the output stages, may be produced.

As techniques for coping with the step difference, the followingtechnique, for example, may be used. Data for correcting the differencein characteristics among plural output stages, such as gain difference,are acquired prior to shipment of the camera 10 from a plant. As themethod for acquiring the data, a light source of a preset light volumeis shot by the camera, and measurement is made of the output value ofthe signal charges G of the output stages 60, 62. Coefficient data forproviding for the same output values of the output stages 60 and 62 arecalculated and held in a non-volatile memory in the camera 10. Inpost-shipment correction, the signal processor 26 reads out thecoefficient data stored in the memory, and multiplies the coefficientdata by output values of the output stages 60 and 62 to correct the gaindifference. This provides for the same output values of the signalcharges G.

The entire disclosure of Japanese patent application Nos. 2006-094407,2006-094567, 2006-095198 and 2006-095374, all filed on Mar. 30, 2006,including the specifications, claims, accompanying drawings andabstracts of the disclosure is incorporated herein by reference in theentirety thereof.

While the present invention has been described with reference to theparticular illustrative embodiments, it is not to be restricted by theembodiments. It is to be appreciated that those skilled in the art canchange or modify the embodiments without departing from the scope andspirit of the present invention.

What is claimed is:
 1. A solid state imaging apparatus comprising: acolor filter for color separating the incident light from a field beingviewed into a plurality of colors; a plurality of photosensitive cellsfor photo-electrically transducing the light transmitted through saidcolor filter, said photosensitive cells being arranged in register withthe colors; a first transfer circuit for transferring signal chargesread out from said photosensitive cells in a first direction; a secondtransfer circuit for transferring signal charges transferred in saidfirst transfer circuit in a second direction; a branching circuitarranged at an output end of said second transfer circuit fordistributing the signal charges transferred to a plurality of outputdestinations; a plurality of third transfer circuits connected as theoutput destinations to said branching circuit; and output circuitsconnected to an output end of said third transfer circuits; said pluralcolors being divided into a plurality of groups; said second transfercircuit, said branching circuit and said third transfer circuitstransferring signal charges read out from the photosensitive cellsrelated with colors of the same group, and subsequently transferringsignal charges read out from the photosensitive cells related withcolors of a different group or groups.
 2. The solid state imagingapparatus in accordance with claim 1 wherein the plural colors are threecolors of red, green and blue, and the groups are two groups, one beinga group composed of red and blue and the other being a group composed ofgreen.
 3. The solid state imaging apparatus in accordance with claim 1wherein, in case there are a plurality of colors belonging to one ofsaid groups, the signal charges read out from the photosensitive cellsrelated with the colors are transferred using a plurality of said thirdtransfer circuits; in case there is one color belonging to one of saidgroups, the signal charges read out from the photosensitive cellsrelated with the color being transferred using a specified one of saidthird transfer circuits.
 4. The solid state imaging apparatus inaccordance with claim 1 wherein, in case there are a plurality of colorsbelonging to one of said groups, the signal charges read out from thephotosensitive cells related with said colors are transferred using aplurality of said third transfer circuits; in case there is one colorbelonging to one of said groups, the signal charges read out from thephotosensitive cells related with the color being also transferred usinga plurality of said third transfer circuits.
 5. The solid state imagingapparatus in accordance with claim 3 wherein, in case there are aplurality of colors belonging to one of said groups, the signal chargesread out from the photosensitive cells related with the colors aretransferred using a specified one of said third transfer circuits fromone color to another.
 6. The solid state imaging apparatus in accordancewith claim 1 further comprising a correction circuit for correcting thedifference in characteristics among said output circuits.
 7. The solidstate imaging apparatus in accordance with claim 6 further comprising: aholding circuit for holding data for correcting the difference incharacteristics among said output circuits; said correction circuitcorrecting the difference in characteristics using data owned by saidholding circuit.
 8. The solid state imaging apparatus in accordance withclaim 1 wherein said first transfer circuit transfer the signal charges,readout from the photosensitive cells, related with the color belongingto the same group, to said second transfer circuit, and subsequentlytransfer signal charges read out from the photosensitive cells relatedwith the color belonging to the different group.
 9. An imaging methodcomprising the steps of: color-separating incident light from a fieldbeing imaged by a color filter; photo-electrically transducing the lighttransmitted through said color filter by a plurality of photosensitivecells related with the colors; transferring signal charges read out fromsaid photosensitive cells by first transfer circuit in a firstdirection; transferring the signal charges transferred by said firsttransfer circuits, by a second transfer circuit in a second direction;distributing the signal charges transferred to a plurality of outputdestinations, by a branching circuit arranged at an output end of saidsecond transfer circuit; and outputting the signal charges by aplurality of third transfer circuits, connected as output destinationsto said branching circuit, and by output circuits arranged at an outputend of said third transfer circuits; said plural colors being groupedinto a plurality of groups; and said second transfer circuit, saidbranching circuit and the third transfer circuits transferring thesignal charges read out from the photosensitive cells related with thecolor belonging to the same group, and subsequently transferring signalcharges read out from the photosensitive cells related with the colorbelonging to the different group.
 10. An imaging method comprising thesteps of: color-separating incident light from a field being imaged by acolor filter; photo-electrically transducing the light transmittedthrough said color filter by a plurality of photosensitive cells relatedwith the colors; transferring signal charges read out from saidphotosensitive cells by first transfer circuit in a first direction;transferring the signal charges, transferred by said first transfercircuit, by a second transfer circuit in a second direction; andoutputting signal charges via an output circuit arranged at an outputend of said second transfer circuit; said plural colors being groupedinto a plurality of groups; and said second transfer circuitstransferring the signal charges read out from the photosensitive cellsrelated with the color belonging to the same group, and subsequentlytransferring signal charges read out from the photosensitive cellsrelated with the color belonging to the different group.